Abstract: Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.

Abstract: Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition.

Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.

Abstract: A semiconductor structure has a substrate having a trench, an isolation dielectric in the trench, and a stress buffer layer, between the substrate and the dielectric. Semiconductor devices containing the semiconductor structure may have higher reliability, and may have a reduced manufacturing costs per device.

Abstract: A magnetic element and a method for making a magnetic element. The method includes patterning a first electrode material to form a first electrode on a substrate and depositing filler material on the substrate around the first electrode. The method further includes polishing to form a planar surface of filler and the first electrode. A magnetic cell is formed on the planar surface and a second electrode is formed on the magnetic cell. In some embodiments, the first electrode has an area that is at least 2:1 to the area of the magnetic cell.

Abstract: Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.

Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

Abstract: Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal.

Abstract: Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and method for low temperature physical vapor deposition (PVD) of an amorphous thin film layer of material onto a substrate. A PVD chamber is configured to support a substrate and has a cathode target with a layer of sputtering material thereon, an anode shield, and a magnetron assembly adjacent the target. A high impulse power magnetron sputtering (HiPIMS) power supply is coupled to the PVD chamber, the power supply having a charging circuit and a charge storage device. The power supply applies relatively high energy, low duty cycle pulses to the magnetron assembly to sputter, via self ionizing plasma, relatively low energy ions from the layer of sputtering material to deposit an amorphous thin film layer onto the substrate.

Abstract: A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.

Abstract: A method of making a memory cell or magnetic element by using two hard masks. The method includes first patterning a second hard mask to form a reduced second hard mask, with a first hard mask being an etch stop for the patterning process, and then patterning the first hard mask to form a reduced first hard mask by using the reduced second hard mask as a mask and using an etch stop layer as an etch stop. After patterning both hard masks, then patterning a functional layer by using the reduced first hard mask as a mask. In the resulting memory cell, the first hard mask layer is also a top lead, and the diameter of the first hard mask layer is at least essentially the same as the diameter of the etch stop layer, the adhesion layer, and the functional layer.

Abstract: Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.

Abstract: A magnetic element and a method for making a magnetic element. The method includes patterning a first electrode material to form a first electrode on a substrate and depositing filler material on the substrate around the first electrode. The method further includes polishing to form a planar surface of filler and the first electrode. A magnetic cell is formed on the planar surface and a second electrode is formed on the magnetic cell. In some embodiments, the first electrode has an area that is at least 2:1 to the area of the magnetic cell.

Abstract: Memory elements and methods for making memory elements. One method of making a memory element includes forming a first electrode, forming an electrically conductive current densifying element and a memory cell on the first electrode, the memory cell and the current densifying element adjacent to each other. A second electrode is formed over the current densifying element and the memory cell. The memory elements may be resistance random access memory elements.

Abstract: A method of forming a semiconductor structure is described that includes etching a first metal layer at the bottom of a via in a first insulating layer to expose a second metal layer, wherein the first metal layer is on the second metal layer, and wherein the etching of the first metal layer is not reactive-ion etching. Methods of making semiconductor devices and electronic devices are also described.

Abstract: A process for making a semiconductor structure, includes forming a second dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes: a semiconductor substrate having the regions, a first dielectric layer on at least a first portion of the semiconductor substrate, an etch-stop layer on at least a second portion of the first dielectric layer, and spacers on at least a third portion of said semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.

Abstract: A process for making a semiconductor structure, includes forming a second dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes: a semiconductor substrate having the regions, a first dielectric layer on at least a first portion of the semiconductor substrate, an etch-stop layer on at least a second portion of the first dielectric layer, and spacers on at least a third portion of said semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.

Abstract: The surface of a borophosphosilicate glass (BPSG) dielectric film undergoes a surface treatment, such as by plasma treatment with N.sub.2 O, N.sub.2 +NH.sub.3, N.sub.2, O.sub.2 or O.sub.3. Erosion caused by H.sub.2 SO.sub.4 boiling or by humidity absorption from the atmosphere is thereby reduced so that reflow processing at temperatures ideally below 850.degree. C. is possible and an interlayer dielectric film of excellent planarity is thus formed.