Abstract: Disclosed is a tape dispenser for cutting tape, while the tape is being unwound by rotation of a tape roll, including: a fixing part coming into close contact with an outer peripheral surface of the tape roll so as to fix the tape roll thereto; a fixing lever to which a given force is applied so that the fixing part rotates to come into close contact with the outer peripheral surface of the tape roll; a rotating shaft connected to the fixing lever and rotating to come into close contact with the outer peripheral surface of the tape roll; an extended part for connecting the fixing part and the rotating shaft with each other; and a close-fitting member disposed on the inner side of the tape roll so as to apply a given force to the tape roll in one direction.

Abstract: A multi-division type tape cutter is disclosed. A multi-division type tape cutter according to the present invention includes: a rotating member which has a cylindrical shape and includes a fastening protrusion provided on one side surface thereof and a plurality of rotating wings provided along the outer cylindrical circumferential surface thereof, each of the rotating wings having a ¬-shaped end; a tape roller into which a tape is fitted; a housing forming a body, wherein the rotating member and the tape roller are fixed to the inside of the housing, a first cutter unit located between the rotating member and the tape roller and provided in a direction orthogonal to a winding direction of the tape; and a second cutter unit provided inside the housing in a direction orthogonal to the winding direction of the tape.

Abstract: Disclosed is a tape dispenser for cutting tape, while the tape is being unwound by rotation of a tape roll, including: a fixing part coming into close contact with an outer peripheral surface of the tape roll so as to fix the tape roll thereto; a fixing lever to which a given force is applied so that the fixing part rotates to come into close contact with the outer peripheral surface of the tape roll; a rotating shaft connected to the fixing lever and rotating to come into close contact with the outer peripheral surface of the tape roll; an extended part for connecting the fixing part and the rotating shaft with each other; and a close-fitting member disposed on the inner side of the tape roll so as to apply a given force to the tape roll in one direction.

Abstract: Provided is a tape dispenser that easily cuts a tape. A tape dispenser includes a drum mounted with a tape roll, a frame supporting the drum, a guide roller rotatably disposed in the frame and guiding a tape at a front side of the drum, and a cutter blade disposed at a front end of a support of the frame and cutting the tape. Here, the cutter blade includes side ends extending in a tape extending direction from a front end on which a plurality of cutting protrusions are formed, and the front end of the cutter blade inclines with respect to the side ends.

Abstract: Provided is a tape dispenser that easily cuts a tape. A tape dispenser includes a drum mounted with a tape roll, a frame supporting the drum, a guide roller rotatably disposed in the frame and guiding a tape at a front side of the drum, and a cutter blade disposed at a front end of a support of the frame and cutting the tape. Here, the cutter blade includes side ends extending in a tape extending direction from a front end on which a plurality of cutting protrusions are formed, and the front end of the cutter blade inclines with respect to the side ends.

Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.

Abstract: Disclosed are a substrate support apparatus and an apparatus for examining the seal pattern of an LCD cell. The substrate support apparatus includes a movable stage provided with drawing nozzles for attaching a substrate to an upper surface and adapted to rotate by a predetermined angle; a fixed stage spaced from the movable stage and provided with floating nozzles for ejecting air upward and drawing nozzles for drawing air downward; and a driving device coupled to the movable stage to rotate the movable stage. The apparatus for examining the seal pattern of an LCD cell includes the substrate support apparatus; and a gantry unit including support platforms positioned on both sides of the substrate support apparatus, a bridge positioned above the substrate support apparatus to connect the support platforms, and a correction device coupled to the bridge to examine and repair a seal pattern of a substrate.

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

Abstract: A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure. The vertical transistor includes a gate electrode and a semiconductor pillar, and the buried wiring is one of source electrode or a drain electrode of the vertical transistor.

Abstract: A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween.

Abstract: A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.

Abstract: An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.

Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

Abstract: A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line.

Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

Abstract: In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.