Abstract: The present invention relates to a derivative compound in which a biphenyl group is introduced into an aminoalkanoic acid, a stereoisomer thereof, or a pharmaceutically acceptable salt thereof. The compound of the present invention exhibits excellent antifungal and fungicidal effects. Furthermore, the compound of the present invention exhibits a synergistic effect when used in combination with a conventional antifungal agent. Furthermore, the compound of the present invention provides broad-spectrum antifungal activity against a wide range of fungal pathogens. Therefore, the compound of the present invention may be widely used in fields requiring treatment with antifungal or fungicidal agents against human pathogenic fungi and animal pathogenic fungi, and phytopathogenic fungi.

Abstract: A printed circuit board includes a first insulating layer; a connection via penetrating through at least a portion of the first insulating layer and having an upper surface exposed to an upper surface of the first insulating layer; a cavity penetrating through at least a portion of the first insulating layer and having the upper surface of the first insulating layer as a bottom surface of the cavity; a bridge disposed in the cavity and having a first bridge pad disposed on a lower side of the bridge; and a bonding layer including conductive particles connected to the connection via and the first bridge pad.

Abstract: The present disclosure relates to a printed circuit board including, a first insulating layer, a first metal layer disposed on the first insulating layer, a bridge disposed on the first metal layer and including a bridge insulating layer and a bridge circuit layer, a second insulating layer disposed on the first insulating layer and covering at least a portion of the bridge, a second metal layer disposed on the second insulating layer, and a connecting via penetrating the bridge and the second insulating layer to connect the first metal layer to the second insulating layer. The connecting via is spaced apart from the bridge circuit layer.

Abstract: A printed circuit board includes a substrate, a first pad and a second pad, respectively disposed on an upper side of the substrate, a first socket disposed in the substrate and including a first circuit, and a first trace disposed in the substrate and disposed between the first and second pads and the first socket with respect to a lamination direction. At least a portion of the first circuit is electrically connected to each of the first and second pads, and is electrically connected to the second pad through a path passing through the first trace.

Abstract: A printed circuit board includes: a bridge including a first insulating material, a wiring pattern disposed in the first insulating layer, a metal post disposed on the first insulating material and connected to the wiring pattern, and a second insulating material disposed on the first insulating material and covering at least a portion of the metal post; a first build-up insulating material disposed around the bridge; and a first redistribution pattern disposed on the second insulating material and the first build-up insulating material and including a metal pad connected to the metal post.

Abstract: A printed circuit board includes a first substrate portion including a first insulating layer and a first wiring layer; and a second substrate portion disposed on the first substrate portion and including a second insulating layer, a pad disposed on the second insulating layer, and a first via penetrating through the second insulating layer and connecting the first wiring layer and the pad to each other. The first via has a boundary with each of the first wiring layer and the pad, and includes a first metal layer and a second metal layer disposed on different levels.

Abstract: A printed circuit board includes: a substrate layer in which a plurality of insulating layers and a plurality of wiring patterns are repeatedly layered, the substrate layer including a conductive via layer disposed in one of the plurality of insulating layers to connect wiring patterns, among the plurality of wiring patterns, disposed on upper and lower surfaces of the one insulating layer, respectively; an uppermost substrate layer including an outermost insulating layer disposed outermost within the substrate layer, and a first wiring pattern disposed in the outermost insulating layer; and a bump pad disposed on a portion of an upper surface of the first wiring pattern and having a length shorter than a length of the first wiring pattern.

Abstract: An antenna substrate includes: a body having a first surface and a second surface opposing each other and a side surface connecting the first surface and the second surface to each other; an antenna portion disposed on the first surface of the body; and a pad portion disposed in the body, exposed to the side surface of the body, and including a plurality of pad layers connected to each other in a first direction from the second surface of the body toward the first surface of the body. At least one of the plurality of pad layers has a greater width in a second direction than in a third direction perpendicular to the second direction when viewed in the first direction.

Abstract: An electronic component embedded substrate includes a core structure including a first insulating body and core wiring layers and having a cavity and having a stopper layer disposed as a bottom surface; an electronic component disposed in the cavity and attached to the stopper layer; and a build-up structure including a second insulating body covering at least a portion each of the core structure and the electronic component and filling at least a portion of the cavity, and build-up wiring layers wherein the stopper layer has a first region in which a portion of one surface is exposed from the first insulating body and a second region in which the other portion of one surface is covered with the first insulating body, and a surface roughness of one surface of the stopper layer in the first region is greater than that of the stopper layer in the second region.

Abstract: A substrate embedded electronic component package includes a core member having a cavity in which a metal layer is disposed on a bottom surface thereof, an electronic component disposed in the cavity, an encapsulant filling at least a portion of the cavity and covering at least a portion of each of the core member and the electronic component, and a connection structure disposed on the encapsulant and including a first wiring layer connected to the electronic component. A wall surface of the cavity has at least one groove portion protruding outwardly from a center of the cavity, and the groove portion extends to a same depth in the core member as a depth of the cavity.

Abstract: A printed circuit board includes a first insulating layer; a first wiring layer having at least a portion buried in one surface side of the first insulating layer and having at least a portion of one surface exposed from the one surface of the first insulating layer; a metal post disposed on the exposed one surface of at least the portion of the first wiring layer; and a second wiring layer disposed on the other surface of the first insulating layer. A width of a first surface, connected to the exposed one surface of at least a portion of the first wiring layer, of the metal post, is greater than a width of a second surface of the metal post opposing the first surface.

Abstract: A substrate having an electronic component embedded therein includes a core structure including a first insulating body and core wiring layers and having a cavity penetrating through a portion of the first insulating body, an electronic component disposed in the cavity, an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, a wiring layer disposed on the insulating material, and a build-up structure disposed on the insulating material and including a second insulating body and a build-up wiring layer. A material of the first insulating body has a coefficient of thermal expansion (CTE) less than a CTE of the second insulating body, and the insulating material has a CTE less than a CTE of a material of the second insulating body.

Abstract: A chip radio frequency package includes a substrate including a first cavity, first and second connection members, a core member, a radio frequency integrated circuit (RFIC) disposed on an upper surface of the substrate, and a first front-end integrated circuit (FEIC) disposed in the first cavity. The core member includes a core insulating layer and a core via that penetrates the core insulating layer. The first connection member has a structure in which a first insulating layer and a first wiring layer are stacked. The second connection member has a second structure in which a second insulating layer and a second wiring layer are stacked. The RFIC inputs or outputs a base signal and a first radio frequency (RF) signal having a frequency higher than a frequency of the base signal, and the first FEIC inputs or outputs the first RF signal and a second RF signal.

Abstract: A substrate having an electronic component embedded therein includes a core substrate including first and second wiring layers disposed on different levels and one or more insulating layers disposed between the first and second wiring layers, having a cavity in which a stopper layer is disposed on a bottom surface of the cavity, and including a groove disposed around the stopper layer on the bottom surface; an electronic component disposed on the stopper layer in the cavity; an insulating material covering at least a portion of each of the core substrate and the electronic component and disposed in at least a portion of each of the cavity and the groove; and a third wiring layer disposed on the insulating material. The stopper layer protrudes on the bottom surface.

Abstract: A printed circuit board includes: a first insulating layer; a first wiring layer at least partially buried in the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second wiring layer at least partially buried in the second insulating layer; and a cavity penetrating through the second insulating layer and a portion of the first insulating layer and exposing a portion of the upper surface of the first insulating layer as a bottom surface of the cavity. The first wiring layer includes a wiring pattern at least partially exposed from the first insulating layer by the cavity, an upper surface of the wiring pattern has a step structure with the upper surface of the first insulating layer exposed by the cavity, and a lower surface of the wiring pattern is coplanar with a lower surface of the first insulating layer.

Abstract: An antenna substrate includes: a body having a first surface and a second surface opposing each other and a side surface connecting the first surface and the second surface to each other; an antenna portion disposed on the first surface of the body; and a pad portion disposed in the body, exposed to the side surface of the body, and including a plurality of pad layers connected to each other in a first direction from the second surface of the body toward the first surface of the body. At least one of the plurality of pad layers has a greater width in a second direction than in a third direction perpendicular to the second direction when viewed in the first direction.

Abstract: A printed circuit board includes a first substrate portion including a first insulating layer and a first wiring layer; and a second substrate portion disposed on the first substrate portion and including a second insulating layer, a pad disposed on the second insulating layer, and a first via penetrating through the second insulating layer and connecting the first wiring layer and the pad to each other. The first via has a boundary with each of the first wiring layer and the pad, and includes a first metal layer and a second metal layer disposed on different levels.

Abstract: A printed circuit board includes: a first insulating layer; a first wiring layer at least partially buried in the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second wiring layer at least partially buried in the second insulating layer; and a cavity penetrating through the second insulating layer and a portion of the first insulating layer and exposing a portion of the upper surface of the first insulating layer as a bottom surface of the cavity. The first wiring layer includes a wiring pattern at least partially exposed from the first insulating layer by the cavity, an upper surface of the wiring pattern has a step structure with the upper surface of the first insulating layer exposed by the cavity, and a lower surface of the wiring pattern is coplanar with a lower surface of the first insulating layer.

Abstract: A substrate having an electronic component embedded therein includes a core structure including a first insulating body and core wiring layers and having a cavity penetrating through a portion of the first insulating body, an electronic component disposed in the cavity, an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, a wiring layer disposed on the insulating material, and a build-up structure disposed on the insulating material and including a second insulating body and a build-up wiring layer. A material of the first insulating body has a coefficient of thermal expansion (CTE) less than a CTE of the second insulating body, and the insulating material has a CTE less than a CTE of a material of the second insulating body.

Abstract: A printed circuit board includes a first insulating layer; a first wiring layer having at least a portion buried in one surface side of the first insulating layer and having at least a portion of one surface exposed from the one surface of the first insulating layer; a metal post disposed on the exposed one surface of at least the portion of the first wiring layer; and a second wiring layer disposed on the other surface of the first insulating layer. A width of a first surface, connected to the exposed one surface of at least a portion of the first wiring layer, of the metal post, is greater than a width of a second surface of the metal post opposing the first surface.