Patents by Inventor YongGil Lee

YongGil Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7456053
    Abstract: A packaging method for segregating die paddles of a leadframe, includes (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the die paddles are connected to each other by at least one connecting bar; (b) attaching a plurality of dies onto the die paddles; (c) forming a molding compound to encapsulate the dies on the die paddles, and exposing the bottom surface of the connecting bar outside the molding compound; and (d) removing part of the connecting bar so as to segregate the die paddles. The die paddles are thus rendered stable during the steps of die attaching, wire bonding and molding, and the yield is raised.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: November 25, 2008
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yonggill Lee, Kwangwon Koh, Sangyun Lee
  • Patent number: 7408244
    Abstract: A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: August 5, 2008
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yonggill Lee, Sangbae Park
  • Publication number: 20070254406
    Abstract: A method for manufacturing a stacked package structure is disclosed, comprising: forming a first chip package structure, comprising: providing a chip carrier having a first and a second surface in opposition to each other; forming bonding wires on the first surface; providing at least one chip on and electrically connected to the first surface; and forming an encapsulant covering the first surface, the chip and the bonding wires, wherein a top end of each bonding wire is exposed at a surface of the encapsulant; forming a plurality of electrical connections respectively deposed on the top end of each bonding wire; and providing a second chip structure electrically jointed with the electrical connections and stacked on the first chip package structure.
    Type: Application
    Filed: June 28, 2007
    Publication date: November 1, 2007
    Inventor: Yonggill Lee
  • Patent number: 7242081
    Abstract: A stacked package structure and a method for manufacturing the same are disclosed. The package structure comprises: a substrate having a first surface and a second surface in opposition to each other; at least one chip deposed on and electrically connected to the first surface of the substrate; a plurality of electrical connection devices deposed on the first surface and periphery of the substrate, wherein each electrical connection device is higher than the at least one chip in altitude; and an encapsulant covering the first surface of the substrate, the at least one chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the encapsulant.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: July 10, 2007
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: Yonggill Lee
  • Patent number: 7169651
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: January 30, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won
  • Publication number: 20070020802
    Abstract: The present invention relates to a packaging method for segregating die paddles of a leadframe. The method comprising: (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the die paddles are connected to each other by at least one connecting bar; (b) attaching a plurality of dies onto the die paddles; (c) forming a molding compound to encapsulating the dies on the die paddles, and exposing the bottom surface of the connecting bar outside the molding compound; and (d) removing part of the connecting bar so as to segregate the die paddles, Whereby the die paddles are stable during the steps of die attaching, wire bonding and molding, and the yield is raised.
    Type: Application
    Filed: February 22, 2006
    Publication date: January 25, 2007
    Inventors: Yonggill Lee, Kwangwon Koh, Sangyun Lee
  • Publication number: 20060261453
    Abstract: A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.
    Type: Application
    Filed: May 3, 2006
    Publication date: November 23, 2006
    Inventors: Yonggill Lee, Sangbae Park
  • Publication number: 20060255449
    Abstract: The present invention relates to a lid and a package structure having the same. The package structure comprises a first substrate, a first chip, a lid and a second package. The first chip is disposed on and electrically connected to the top surface of the first substrate. The lid is disposed on the top surface of the first substrate and comprises a body, a plurality of through holes and a cavity. The through holes penetrate the body and have a conductive material therein. The cavity accommodates the first chip. The second package is on the lid and is electrically connected to the first substrate through the conductive material in the through holes. As a result, the amount of the signal path between the second package and the first substrate is increased, and the manufacturing cost of the package structure is low.
    Type: Application
    Filed: February 15, 2006
    Publication date: November 16, 2006
    Inventors: Yonggill Lee, Kyungsoo Rho, Taejun Jeong
  • Patent number: 7087461
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 8, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won
  • Publication number: 20060035414
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Application
    Filed: August 11, 2004
    Publication date: February 16, 2006
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won