Patents by Inventor YongGil Lee

YongGil Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097771
    Abstract: The disclosure relates to a method for processing a communication path in a portable communication device, which includes: identifying whether at least some of a plurality of active elements included in a communication circuit disposed between an antenna and a communication processor are in an abnormal state and, based on an abnormal state of a first active element supporting delivery of a signal of a first frequency band among the plurality of active elements being detected, controlling the portable communication device to deliver the signal of the first frequency band based on a second active element different form the first active element among the plurality of active element, and a portable communication device supporting the same.
    Type: Application
    Filed: August 24, 2023
    Publication date: March 21, 2024
    Inventors: Suho JIN, Jaebum BAE, Dongju LEE, Hyeontae CHO, Yonggil HAN, Bongsub KIM, Jinwan AN, Jonghoon WOO, Hyunsuk CHOI
  • Patent number: 7169651
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: January 30, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won
  • Patent number: 7087461
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 8, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won
  • Publication number: 20060035414
    Abstract: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
    Type: Application
    Filed: August 11, 2004
    Publication date: February 16, 2006
    Inventors: HyungJun Park, HyeongNo Kim, SangBae Park, YongGil Lee, KyungSoo Rho, JunYoung Yang, JinHee Won