Abstract: Disclosed is a flow regulating valve. The flow regulating valve includes: a valve body structure, where the valve body structure includes a main body and a sealing seat connected with the main body, the sealing seat is provided with a valve port, and the sealing seat is made of a nonmetallic material; and a valve head movably arranged in a cavity of the main body to close or open the valve port, where the valve head is made of a metal material, and a hardness of the sealing seat is less than a hardness of the valve head.

Abstract: The disclosure provides a valve core assembly and an electronic expansion valve having the valve core assembly. The valve core assembly includes: a valve head, herein an inner wall surface of the valve head is provided with a flange portion which is inwardly protruded, and the flange portion is configured to divide an inner cavity of the valve head into an upper cavity body and a lower cavity body; a screw penetrating into the valve head; and an annular member sleeved at a lower end of the screw and located in the lower cavity body, herein an upper end face of the annular member is in contact with a lower end face of the flange portion. Herein the flange portion is provided with a balancing channel, and the balancing channel connects the upper cavity body and the lower cavity body.

Abstract: A communications server apparatus for managing a request for transport-related services, which is configured to, in response to receiving user request data, generate a data record having a plurality of transit point data fields having data for a corresponding plurality of transit points from an origin to a destination, including a variable transit point data field having data that is determined based on data associated with at least one transportation network-related parameter, and having a plurality of trip section data fields for a corresponding plurality of trip sections defining navigation directions from the origin to the destination, and, for each trip section data field, to associate the trip section data field with a respective transit point data field, and, based on the data of the associated transit point data field, to determine a respective transportation mode and to generate transit data in respect of the respective transportation mode.

Abstract: A communications server apparatus for managing a request for transport-related services, which is configured to, in response to receiving user request data, generate a data record having a plurality of transit point data fields having data for a corresponding plurality of transit points from an origin to a destination, including a variable transit point data field having data that is determined based on data associated with at least one transportation network-related parameter, and having a plurality of trip section data fields for a corresponding plurality of trip sections defining navigation directions from the origin to the destination, and, for each trip section data field, to associate the trip section data field with a respective transit point data field, and, based on the data of the associated transit point data field, to determine a respective transportation mode and to generate transit data in respect of the respective transportation mode.

Abstract: A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.

Abstract: Embodiments of the present disclosure may include receiving, at one or more computing devices, the electronic circuit design, wherein the electronic circuit design includes at least one Unified Power Format file. Embodiments may further include generating, using the one or more computing devices, a schematic of a power supply network, based upon, at least in part, the at least one Unified Power Format file, the schematic including one or more power supply network components.

Abstract: A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.

Abstract: A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.

Abstract: A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

Abstract: Method, apparatus, and computer readable medium for simulating a logic design having power domains are described. In some examples, a switchable power domain of the power domains is identified, the switchable power domain having primary inputs and having a power state switchable between a power-on state and a power-off state. The logic design is traversed to analyze driver and load logic of each of the primary inputs to the switchable power domain to identify any pure pass-through nets each of which has no driver and no load logic in the switchable power domain.

Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Abstract: Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in the RTL design environment, where the plurality of power domains are controlled by a set of power control signals through a power manager logic, isolating a power domain among the plurality of power domains for simulation, and simulating isolation behavior of the power domain in response to variations in power applied to the power domain.

Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Abstract: Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in the RTL design environment, where the plurality of power domains are controlled by a set of power control signals through a power manager logic, isolating a power domain among the plurality of power domains for simulation, and simulating isolation behavior of the power domain in response to variations in power applied to the power domain.