Patents by Inventor Yonghao Chen

Yonghao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for simulating state retention of an RTL design
    Patent number: 7610571
    Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: October 27, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Yonghao Chen
  • Simulation of power domain isolation
    Patent number: 7596769
    Abstract: Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in the RTL design environment, where the plurality of power domains are controlled by a set of power control signals through a power manager logic, isolating a power domain among the plurality of power domains for simulation, and simulating isolation behavior of the power domain in response to variations in power applied to the power domain.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: September 29, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Yonghao Chen
  • Method and system for simulating state retention of an RTL design
    Publication number: 20070245277
    Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.
    Type: Application
    Filed: July 18, 2006
    Publication date: October 18, 2007
    Inventor: Yonghao Chen
  • Method and mechanism for implementing electronic designs having power information specifications background
    Publication number: 20070245285
    Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
    Type: Application
    Filed: October 30, 2006
    Publication date: October 18, 2007
    Inventors: Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Manish Pandey, Huan-Chih Tsai, Sandeep Bhatia, Yonghao Chen, Steven Sharp, Vivek Chickermane, Patrick Gallagher
  • Simulation of power domain isolation
    Publication number: 20070245278
    Abstract: Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in the RTL design environment, where the plurality of power domains are controlled by a set of power control signals through a power manager logic, isolating a power domain among the plurality of power domains for simulation, and simulating isolation behavior of the power domain in response to variations in power applied to the power domain.
    Type: Application
    Filed: July 18, 2006
    Publication date: October 18, 2007
    Inventor: Yonghao Chen