Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral.

Abstract: A system and method for configuring capacitive sensing speed are provided. In one example, a circuit includes first and second circuitry and control logic. The first circuitry controls a first current provided to a reference capacitor having a known capacitance. The second circuitry controls a second current to an external capacitor having an unknown capacitance. The control logic is configured to receive input defining a period of time at which to set the charge time of the reference capacitor, control the first circuitry to provide a minimum amount of the first current needed to charge the reference capacitor within the defined period of time, and control the second circuitry to provide an amount of the second current needed to normalize the charge time of the external capacitor with the charge time of the reference capacitor.

Abstract: A microcontroller unit having a suspend mode of operation includes a processing circuit for receiving digital information and processing said received digital information. Timing circuitry generates timing signals to the processing circuit responsive to signals received from a clock circuit which generates both an internal clock signal and an external clock signal. Circuitry for controlling the selective application of a synchronized enable signal and the external clock signal to the timing circuitry. The circuitry applies the internal clock signal to the timing circuitry in at least an active mode of operation of the microcontroller unit responsive to at least one first control signal and applies the external clock signal to the timing circuitry in at least a suspend mode of operation of the microcontroller unit responsive to at least one suspend control signal.

Abstract: A microcontroller unit having a suspend mode of operation includes a processing circuit for receiving digital information and processing said received digital information. Timing circuitry generates timing signals to the processing circuit responsive to signals received from a clock circuit which generates both an internal clock signal and an external clock signal. Circuitry for controlling the selective application of a synchronized enable signal and the external clock signal to the timing circuitry. The circuitry applies the internal clock signal to the timing circuitry in at least an active mode of operation of the microcontroller unit responsive to at least one first control signal and applies the external clock signal to the timing circuitry in at least a suspend mode of operation of the microcontroller unit responsive to at least one suspend control signal.