Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers and having a cavity penetrating through a portion of the plurality of insulating layers, a passive component disposed in the cavity and including an external electrode electrically connected to at least one of the plurality of wiring layers, and a bridge disposed on the passive component in the cavity and including one or more circuit layers electrically connected to the external electrode.

Abstract: Disclosed are wire clamps and wire bonding apparatuses including the same. The wire clamp comprises a clamping lever, a driving lever parallel to the clamping lever and having an upper support, a shaft that penetrates a center of the driving lever to connect to the clamping lever, a spring in the driving lever and on an outer circumferential surface of the shaft, and an upper pivot that protrudes from an inner wall of the upper support to separate the upper support from the clamping lever. The driving lever has a load point and an effort point on opposite sides of the shaft. The effort point is connected in a direction of a straight line to the shaft and the effort point.

Abstract: A device for selectively removing a perfluorinated compound may include an adsorption electrooxidation tank including a reaction unit having a plurality of electrodes and granular activated carbon configured to oxidize and decompose a perfluorinated compound in raw water through adsorption and electrooxidation, a power supply device configured to supply power to the adsorption electrooxidation tank, and a head adjustment pipe unit configured to maintain a water level within the reaction unit at a height greater than or equal to a reaction height of the electrode.

Abstract: Disclosed are a terminal, an operating method thereof, and a computer-readable recording medium. The operating method includes establishing a video call session between a first terminal and a second terminal, receiving, by the second terminal, data obtained by the first terminal, sequentially storing, by the second terminal, the data received from the first terminal in a buffer size, performing, by the second terminal, a validity check on the data stored in the buffer, and processing, by the second terminal, the data in response to a result of the validity check.

Abstract: Disclosed are a terminal, an operating method thereof, and a computer-readable recording medium. The operating method includes establishing a video call session between a first terminal and a second terminal, receiving, by the second terminal, data obtained by the first terminal, sequentially storing, by the second terminal, the data received from the first terminal in a buffer size, performing, by the second terminal, a validity check on the data stored in the buffer, and processing, by the second terminal, the data in response to a result of the validity check.

Abstract: A method of providing a video stream based on machine learning in an electronic device according to various example embodiments may include receiving a source video stream which is streamed from a first device to at least one other device, confirming whether an event is detected on the source video stream using a learning model trained through machine learning on the basis of at least one frame of the source video stream, and determining whether to restrict streaming of the source video stream from the first device on the basis of the event detection. In addition to the method, other example embodiments are possible.

Abstract: A method for generating and validating customized investment portfolios according to an example of the present invention includes (a) a step of receiving an investment idea from a user terminal; (b) a step of selecting an investment product corresponding to the investment idea, and selecting an asset investment ratio distribution method for each investment product to generate the investment portfolio; (c) a step of validating risk and profitability of the investment portfolio in accordance with a past period and predetermined criteria, and providing generation results and validation results of the investment portfolio to the user terminal; and (d) a step of setting the investment portfolio to be exposed to another user terminal connected to the server in accordance with a request of the user terminal.

Abstract: Disclosed are a terminal, an operating method thereof, and a computer-readable recording medium. The operating method includes establishing a video call session between a first terminal and a second terminal, receiving, by the second terminal, data obtained by the first terminal, sequentially storing, by the second terminal, the data received from the first terminal in a buffer size, performing, by the second terminal, a validity check on the data stored in the buffer, and processing, by the second terminal, the data in response to a result of the validity check.

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A bonding wire includes a wire core including a silver-palladium alloy. A coating layer is disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

Abstract: A semiconductor device includes a first device having a first pad; a second device having a second pad; and a bonding wire electrically connecting the first device and the second device to each other via the first pad and the second pad. The bonding wire includes: a first bonding structure provided at a first end of the bonding wire, electrically connected to the first device and includes: a first ball bonding region; and a first stitch bonding region; and a second bonding structure provided at a second end opposite of the first end of the bonding wire and electrically connected to the second device.

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A bonding wire includes a wire core including a silver-palladium alloy, and a coating layer disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.

Abstract: A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Abstract: A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.