Abstract: A vehicle includes a sound absorption sheet. The sound absorption sheet includes a plurality of resonance units connected into a single sheet, and each of the plurality of resonance units includes a unit base, a neck, a sound absorption cavity being formed inside the unit base, and a through hole being arranged on the unit base. The neck is arranged in the sound absorption cavity. The neck has a tubular structure. A first end of the neck includes a first opening, and a second end of the neck includes a second opening. The first opening is connected to the through hole and is in communication with the outside. The second end of the neck is located inside the sound absorption cavity, and the second opening is in communication with the sound absorption cavity.

Abstract: Disclosed are a synchronous triggering system, a quantum control system and a quantum computer. The synchronous triggering system comprises a central control device, several routing boards and several functional boards. It guarantees the synchronous triggering of the triggering signals by means of a three-stage triggering synchronization system. In the first stage, the central control device provides several sets of triggering signals to corresponding routing boards, and adjusts an initial time point for each set of triggering signals to output so that each chassis receives the triggering signals concurrently. In the second stage, communication lines from each routing board to the several functional boards are of equal length. In the third stage, the triggering signals arrive at several data-processing devices simultaneously after being processed under the AND-operation of an AND-gate chip.

Abstract: Embodiments of the disclosure provide a quantum chip system, a quantum computing processing system and an electronic apparatus, wherein one quantum chip system includes at least one first qubit, each first qubit includes at least two control electrodes, and a first event register for controlling the control electrode, wherein each first event register is configured for storing a control signal of the control electrode, and each first qubit corresponds to at least two first event registers.

Abstract: In an application development system, a first electronic device sends an original installation package of a target application to a server. The original installation package of the target application indicates a function and/or a page layout corresponding to at least one type of device information. The server determines at least one target installation package based on the original installation package. The at least one target installation package one-to-one corresponds to the at least one type of device information. The server receives a first download request sent by a second electronic device, and sends a first installation package to it; the server receives a second download request sent by a third electronic device, and sends a second installation package to it. The first installation package and second installation package are a target installation package corresponding to device information of the second electronic device and third electronic device respectively.

Abstract: Disclosed are a quantum state information processing system, a quantum measurement and control system, and a quantum computer. In this system, a sampling module is used to perform sampling processing on an analog signal collected from a qubit, a frequency mixing module is used to perform mixing processing on the sampled signal, a demodulation module is used to perform demodulation processing on a mixed signal, and a determining module is used to perform state classification on a demodulated signal by using a state classification equation, so as to acquire quantum state information.

Abstract: Disclosed are a probe apparatus, and a measurement method and a measurement system of a junction resistance of a superconducting qubit. The probe apparatus is configured to measure a superconducting quantum chip, and includes a probe set, a probe control mechanism, and a power supply module; the probe set includes two probes that are independent; the probe control mechanism is configured to control the probe set to be connected to an oxide layer on a surface of an electrode of a Josephson junction on the superconducting quantum chip; and the power supply module is configured to apply an electrical breakdown signal to two probes, to break down the oxide layer, so that the probe set forms a conductive connection with the electrode of the Josephson junction.

Abstract: The present disclosure relates to service data transmission methods and devices. One example method includes establishing a first Bluetooth logical channel with a first main control chip of a wearable device and a second Bluetooth logical channel with a second main control chip of the wearable device, where the first main control chip and the second main control chip have different processing capabilities and energy consumption, and sending, based on an interaction channel corresponding to a service, service data to the first main control chip through the first Bluetooth logical channel or to the second main control chip through the second Bluetooth logical channel.

Abstract: In a message processing method, after receiving a message from a second electronic device, a first electronic device controls, using a microcontroller unit (MCU), a display of the first electronic device to display the message. Then, the first electronic device obtains an operation performed on the message and processes, using the MCU, the operation when the operation is a first operation type.

Abstract: A mask fabrication method, mask, Josephson junction element, and quantum chip is provided, which belong to the field of quantum information, especially the field of quantum computing. The mask fabrication method includes: providing a dielectric layer, wherein a ratio of a thickness of the dielectric layer to a line width of a target pattern to be fabricated is greater than a cutting depth-to-width ratio allowed by a patterning apparatus; determining a first sublayer and a second sublayer of the dielectric layer, wherein a ratio of a thickness of the second sublayer to the line width of the target pattern is less than or equal to the cutting depth-to-width ratio; forming the target pattern on the second sublayer and a first pattern on the first sublayer, wherein the first pattern exposes the target pattern.

Abstract: Disclosed are a quantum chip test structure and a fabrication method therefor, and a test method and a fabrication method for a quantum chip. The quantum chip test structure includes: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, where a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, where a deposition window is formed in the second isolation layer; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, and the electrical connection layer is configured to implement electrical contact with a test device.

Abstract: Disclosed are a carrier transport simulation method, a carrier transport simulation apparatus, a medium, and an electronic device. A physical simulation model, and an initial condition and/or a boundary condition for carrier transport in a semiconductor device are determined; a mathematical physical equation correspondingly for solving the physical simulation model is determined; and a carrier density in the semiconductor device is determined based on the initial condition and/or the boundary condition, and the mathematical physical equation, to implement a simulation of carrier transport in the semiconductor device, so as to implement a simulation of carrier transport in a semiconductor device.

Abstract: A quantum device includes: a quantum chip, provided with an I/O port; and a superconducting substrate, provided with transmission lines on the superconducting substrate. Each of the transmission lines includes a first section and a second section that form an included angle, a bonding connection structure is formed between one end of the first section and the I/O port, a pad for connecting to a connector is formed at one end of the second section, and a distribution spacing between the first sections is smaller than a distribution spacing between the second sections. The second sections are distributed in a region away from the quantum chip. The first section connected to the 1/0 port via aluminum wire bonding can be wired at higher density. The size of the pad on a wiring spacing is reduced, and density of the transmission lines on the superconducting substrate is increased.

Abstract: Disclosed are a superconducting quantum chip structure and a fabrication method for a superconducting quantum chip. The superconducting quantum chip structure includes a first structural member, a second structural member, and a support and connection member, where the first structural member is provided with a qubit, a read cavity, and a first connection terminal, the qubit is coupled to the read cavity, and the qubit is electrically connected to the first connection terminal; the second structural member is provided with a signal transmission line and a second connection terminal electrically connected to each other; and two ends of the support and connection member are electrically connected to the first connection terminal and the second connection terminal, respectively, and the support and connection member is configured to transmit a control signal received on the signal transmission line to the qubit.

Abstract: Disclosed are a quantum chip test structure and a fabrication method therefor, and a test method and a fabrication method for a quantum chip. The quantum chip test structure includes: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, where a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, where a deposition window is formed in the second isolation layer; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, and the electrical connection layer is configured to implement electrical contact with a test device.

Abstract: Embodiments of the present specification provide a quantum chip controller, a quantum computing processing system, and an electronic apparatus. The quantum chip controller includes: an instruction execution unit for executing a quantum instruction to generate a quantum event and its corresponding time point; and a quantum chip queue control unit including: an event queue for storing a quantum event to be executed, a time queue for storing a time point corresponding to the quantum event to be executed, and a time counter for counting time, wherein when time being counted in the time counter is equal to a time point in the time queue, a quantum event corresponding to the time point is read out from the event queue and is to be executed by a quantum chip, and wherein the time counter includes an enabling control section for controlling starting and pausing of counting of the time counter.

Abstract: Embodiments of the disclosure provide a quantum chip system, a quantum computing processing system and an electronic apparatus, wherein one quantum chip system includes at least one first qubit, each first qubit includes at least two control electrodes, and a first event register for controlling the control electrode, wherein each first event register is configured for storing a control signal of the control electrode, and each first qubit corresponds to at least two first event registers.

Abstract: The present disclosure provides an active noise reduction method, a system, and a new energy vehicle. The active noise reduction method includes: obtaining a frequency of a high-frequency noise signal in an acoustic environment, constructing and generating a harmonic masking signal according to the frequency of the high-frequency noise signal, where the harmonic masking signal includes a harmonic signal and a masking signal, and the harmonic signal is a subharmonic wave of the high-frequency noise signal, and inputting the harmonic masking signal into a sound playback apparatus for playback to output a noise reduction construction sound, and performing noise reduction on the acoustic environment.

Abstract: The present disclosure provides an active noise reduction method, a system, and a new energy vehicle. The active noise reduction method includes: obtaining a frequency of a high-frequency noise signal in an acoustic environment, constructing and generating a harmonic masking signal according to the frequency of the high-frequency noise signal, where the harmonic masking signal includes a harmonic signal and a masking signal, and the harmonic signal is a subharmonic wave of the high-frequency noise signal, and inputting the harmonic masking signal into a sound playback apparatus for playback to output a noise reduction construction sound, and performing noise reduction on the acoustic environment.

Abstract: The present invention provides a side wall of railway wagon and a boxcar of railway wagon. The side wall of the railway wagon comprises an upper side plate, a lower side plate, an inner side stake and an outer side stake, wherein the said inner side stake is arranged at the inner side of the said upper side plate and the said lower side plate, and the said outer side stake is arranged at the upper part of the said side wall of railway wagon and is arranged at the outer side of the said upper side plate. By applying the side wall in the form of internal stakes, the side wall of railway wagon and the boxcar of railway wagon of the present invention can make full use of the width space between the outer surface of the side plate and the outer surface of the side stake on the basis that the external dimension of the railway wagon is not changed, thereby effectively improving the volume of the railway wagon and the transporting capability of the train.