Patents by Inventor Yongjun Hu

Yongjun Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6096640
    Abstract: Disclosed is a gate electrode stack structure that uses a refractory metal silicon nitride layer as a diffusion barrier. The gate electrode stack has several layers, including a gate oxide layer over the semiconductor substrate, a polysilicon layer over the gate oxide layer, and the diffusion barrier between the polysilicon layer and a layer of electrically conductive material above. The diffusion barrier, which is preferably composed of a substantially amorphous refractory metal silicon nitride such as tungsten silicon nitride, does not oxidize when an oxidation process is applied to the gate electrode stack. Moreover, the diffusion barrier substantially prevents diffusion of the electrically conductive material into the polysilicon during heating processes. The refractory metal silicon nitride maintains a bulk resistivity less than 2,000 microhm-cm, thereby preserving satisfactory conductivity in the gate electrode stack.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: August 1, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu
  • Patent number: 6015997
    Abstract: Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: January 18, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Hu, Pai-Hung Pan, Er-Xuan Ping, Randhir P.S. Thakur, Scott DeBoer
  • Patent number: 6004869
    Abstract: A method for forming conductive lines such as interconnects and DRAM gate stacks. A blanket stack is formed on a substrate including a conductive diffusion barrier, a near noble metal such as cobalt, followed by a silicon layer and a top insulator layer. The blanket stack is patterned with resist to define the conductive lines. The stack is dry etched down to the near noble metal layer. The resist is then removed and the stack is annealed to react the near noble metal and silicon to form a conductive compound having fine grain size. The unreacted noble metal is then wet etched, using the conductive diffusion barrier as a wet etch stop. A further dry etch is then performed down to the substrate, using the top insulator layer as a mask. In this manner, only one mask is required to form the conductive line.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: December 21, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu
  • Patent number: 5962904
    Abstract: Disclosed is a gate electrode stack structure that uses a refractory metal silicon nitride layer as a diffusion barrier. The gate electrode stack has several layers, including a gate oxide layer over the semiconductor substrate, a polysilicon layer over the gate oxide layer, and the diffusion barrier between the polysilicon layer and a layer of electrically conductive material above. The diffusion barrier, which is preferably composed of a substantially amorphous refractory metal silicon nitride such as tungsten silicon nitride, of does not oxidize when an oxidation process is applied to the gate electrode stack. Moreover, the diffusion barrier substantially prevents diffusion of the electrically conductive material into the polysilicon during heating processes. The refractory metal silicon nitride maintains a bulk resistivity less than 2,000 microhm-cm, thereby preserving satisfactory conductivity in the gate electrode stack.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: October 5, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu
  • Patent number: 5926730
    Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: July 20, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Hu, Randhir P. S. Thakur, Scott DeBoer
  • Patent number: 5863393
    Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a "graded" stoichiometry of material deposited in the recess.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: January 26, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu
  • Patent number: 5725739
    Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a "graded" stoichiometry of material deposited in the recess.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: March 10, 1998
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu
  • Patent number: 5633200
    Abstract: Disclosed herein is a process for manufacturing a smooth, large grain tungsten nitride film. Under the process, tungsten nitride is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level wherein primarily tungsten is sputtered with only a light nucleation of tungsten nitride being evenly distributed in the tungsten. A separate grain growth step is subsequently conducted in an environment of nitrogen to grow a film of large grain tungsten nitride. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided titanium salicide diffusion barrier with a covering of tungsten nitride. The stack structure is formed in accordance with the tungsten nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: May 27, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Hu