Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Abstract: In a device for evaluating torsional structural performance of girder according to an embodiment of the present disclosure, a guide unit of a support member formed in a shape of an arc having its center that matches a shear center of the girder rotatably supports a rotating member, so that the shear center of the girder matches a center of torsion during clockwise or counterclockwise rotation of the rotating member, thereby measuring an accurate angle of twist and preventing an incident in which the rotating member escapes due to separation of a component by a rotational force.

Abstract: A refill container removably stored in a cosmetic compact includes: a main body being open at an upper part thereof and having a housing space inside thereof, an upper end sealing protrusion part, a lateral sealing protrusion part provided at an outer surface of the inner wall, and an outer wall being provided outside the inner wall with a predetermined gap therebetween; and a mesh fabric cover having a cylindrical first vertical extension part combined with the inner wall and the outer wall by being inserted into a gap provided therebetween such that an inner surface of the first vertical extension part is in close contact with the lateral sealing protrusion part, and a first rim part provided at an upper end of first vertical extension part.

Abstract: In a device for evaluating torsional structural performance of girder according to an embodiment of the present disclosure, a guide unit of a support member formed in a shape of an arc having its center that matches a shear center of the girder rotatably supports a rotating member, so that the shear center of the girder matches a center of torsion during clockwise or counterclockwise rotation of the rotating member, thereby measuring an accurate angle of twist and preventing an incident in which the rotating member escapes due to separation of a component by a rotational force.

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: Disclosed is a refill case detachably accommodated in a cosmetic compact, the refill case including: a main body being configured such that an upper portion thereof is open, and including an inner wall providing an accommodation space in the main body, and an outer wall provided at an outer side of the main body with a predetermined gap between the inner wall and the outer wall; and a mesh fabric cover including a cylindrical vertical extension portion tightly inserted in the gap, a rim portion extending from an upper end of the vertical extension portion in an inward direction, and a mesh fabric configured such that upper and lower surfaces thereof are interposed between the upper end of the vertical extension portion and an outer edge the rim portion along an edge thereof to be integrally provided, thereby covering an upper portion of the accommodation space.

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.

Abstract: A refill container removably stored in a cosmetic compact includes: a main body being open at an upper part thereof and having a housing space inside thereof, an upper end sealing protrusion part, a lateral sealing protrusion part provided at an outer surface of the inner wall, and an outer wall being provided outside the inner wall with a predetermined gap therebetween; and a mesh fabric cover having a cylindrical first vertical extension part combined with the inner wall and the outer wall by being inserted into a gap provided therebetween such that an inner surface of the first vertical extension part is in close contact with the lateral sealing protrusion part, and a first rim part provided at an upper end of first vertical extension part.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and a plurality bit lines to corresponding rows and columns of resistive memory cells in the array. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance associated therewith is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance associated therewith, which is greater than the first parasitic resistance.

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: Disclosed is a refill case detachably accommodated in a cosmetic compact, the refill case including: a main body being configured such that an upper portion thereof is open, and including an inner wall providing an accommodation space in the main body, and an outer wall provided at an outer side of the main body with a predetermined gap between the inner wall and the outer wall; and a mesh fabric cover including a cylindrical vertical extension portion tightly inserted in the gap, a rim portion extending from an upper end of the vertical extension portion in an inward direction, and a mesh fabric configured such that upper and lower surfaces thereof are interposed between the upper end of the vertical extension portion and an outer edge the rim portion along an edge thereof to be integrally provided, thereby covering an upper portion of the accommodation space.

Abstract: The present invention relates to a compact for cosmetics comprising an upper case, a lower case rotatably coupled to the upper case and a refill case detachably received in the lower case, wherein the refill case comprises a case mainbody where contents for cosmetics are received; a case cover which opens and closes the case mainbody; and a mesh screen cover having a border rim part which is received in the case mainbody to be tightly received within a wall of the mainbody, and a high elasticity mesh screen which has a border area supported by the border rim part to extend inwardly so as to cover the contents for cosmetics from an outside. Accordingly, expanded space is provided for receiving contents for cosmetics, the contents for cosmetics is prevented from flowing out of the refill case by the high elasticity mesh screen covering the contents for cosmetics, and the contents for cosmetics is prevented from being directly exposed to the outside thus decreasing vaporization when the case is open.

Abstract: The present invention relates to a compact for cosmetics comprising an upper case, a lower case rotatably coupled to the upper case and a refill case detachably received in the lower case, wherein the refill case comprises a case mainbody where contents for cosmetics are received; a case cover which opens and closes the case mainbody; and a mesh screen cover having a border rim part which is received in the case mainbody to be tightly received within a wall of the mainbody, and a high elasticity mesh screen which has a border area supported by the border rim part to extend inwardly so as to cover the contents for cosmetics from an outside. Accordingly, expanded space is provided for receiving contents for cosmetics, the contents for cosmetics is prevented from flowing out of the refill case by the high elasticity mesh screen covering the contents for cosmetics, and the contents for cosmetics is prevented from being directly exposed to the outside thus decreasing vaporization when the case is open.