Abstract: The present disclosure discloses a three-dimensional photodetector and a method of manufacturing the same. The three-dimensional photodetector according to an embodiment of the present disclosure includes a base part formed in the center region of the three-dimensional photodetector; a first bending part formed around the base part; at least one branch part connected to the base part through the first bending part; second bending parts formed on the at least one branch part; bonding parts connected to the at least one branch part through the second bending parts; at least one photoresistor formed on the surface of at least one of the base part and the branch parts; and a stretchable substrate to which the bonding parts are attached, wherein the bonding parts are attached to the stretchable substrate so that the base part has a gap in the thickness direction of the stretchable substrate; and the at least one photoresistor is responsible for tracking the traveling direction of light.

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.

Abstract: A refill container removably stored in a cosmetic compact includes: a main body being open at an upper part thereof and having a housing space inside thereof, an upper end sealing protrusion part, a lateral sealing protrusion part provided at an outer surface of the inner wall, and an outer wall being provided outside the inner wall with a predetermined gap therebetween; and a mesh fabric cover having a cylindrical first vertical extension part combined with the inner wall and the outer wall by being inserted into a gap provided therebetween such that an inner surface of the first vertical extension part is in close contact with the lateral sealing protrusion part, and a first rim part provided at an upper end of first vertical extension part.

Abstract: A backlight assembly includes an optical member, a bottom chassis that includes a bottom surface on which the optical member is disposed, a first sidewall portion that protrudes from a first side of the bottom surface in a first direction, and a first support portion that protrudes from the first sidewall portion in a second direction that intersects the first direction, and an assembly member that includes a body, and, protruding from the body, a first protrusion and a second protrusion. The second protrusion overlaps an outer surface of the first support portion.

Abstract: The present invention provides a method of performing a position measurement on the basis of a signal from a global navigation satellite system (GNSS). The method includes: receiving initial position information; estimating an initial value of a multipath error through a measurement of the GNSS signal on the basis of the received initial position information; estimating a multipath error from the initial value of the multipath error on the basis of a change in the measurement; removing the estimated multipath error from the measurement of the GNSS signal; and performing the position measurement on the basis of the GNSS measurement from which the multipath error is removed.

Abstract: A method for manufacturing an electrode assembly, in which a plurality of electrodes are stacked, wherein a negative electrode and a positive electrode are sequentially and alternately stacked, and a separator is disposed therebetween is provided. The method includes covering a top surface of an electrode disposed at an n layer (n being a natural number) with the separator, heating the separator covering the electrode disposed at the n layer, stacking an electrode disposed at an n+1 layer on the heated separator, covering a top surface of the electrode disposed at the n+1 layer with the separator, and heating the separator covering the electrode disposed at the n+1 layer. The separator is bonded to the electrode, or the separators are bonded to each other to fix the movement of the electrode, thereby improving stability. Since the separator is not stacked in the width direction, capacity per volume increases.

Abstract: Provided are an image sensor module, an image processing module, and an imaging device including the two modules. The image sensor module includes: a plurality of image sensors: a frame in which the image sensors are mounted to have different imaging angles; and at least one memory configured to store calibration information reflecting distance information generated from images obtained by the image sensors, respectively.

Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.

Abstract: A memory device includes: a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells includes a switching element, and a data storage element connected to the switching element, wherein the data storage element includes a phase change material; and a memory controller configured to perform a control operation with respect to a first memory cell of the plurality of memory cells by inputting an operating current to the first memory cell, and inputting a compensation current flowing from the data storage element to the switching element in the first memory cell before or after inputting the operating current to the first memory cell.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: The present disclosure discloses a three-dimensional photodetector and a method of manufacturing the same. The three-dimensional photodetector according to an embodiment of the present disclosure includes a base part formed in the center region of the three-dimensional photodetector; a first bending part formed around the base part; at least one branch part connected to the base part through the first bending part; second bending parts formed on the at least one branch part; bonding parts connected to the at least one branch part through the second bending parts; at least one photoresistor formed on the surface of at least one of the base part and the branch parts; and a stretchable substrate to which the bonding parts are attached, wherein the bonding parts are attached to the stretchable substrate so that the base part has a gap in the thickness direction of the stretchable substrate; and the at least one photoresistor is responsible for tracking the traveling direction of light.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and a plurality bit lines to corresponding rows and columns of resistive memory cells in the array. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance associated therewith is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance associated therewith, which is greater than the first parasitic resistance.

Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.

Abstract: Provided is a pharmaceutical composition including quercetin-3-O-?-D-xylopyranoside for preventing or treating a liver disease. Since the composition has an effect on inhibiting alcohol-induced accumulation of triglycerides in the blood and liver, having no toxicity and without affecting feed intake, body weight, organ weight, and the like, the composition of the present invention may be efficiently utilized as a pharmaceutical composition for preventing and treating a liver disease such as steatosis, hepatitis, hepatic fibrosis, and cirrhosis or a health functional food for preventing or alleviating a liver disease such as steatosis, hepatitis, hepatic fibrosis, and cirrhosis.

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Abstract: A hydraulic actuator to which a limit-adjustable mechanical lock device is applied, comprising: a housing having a first hole; side covers coupled at both sides of the housing, and having holder insertion holes formed to be opened toward the first hole side of the housing, and plugs; a first holder of which one side of the outer peripheral surface is inserted into the holder insertion hole at the plug side of the side cover by screw coupling; a second holder fitted and coupled to the inner peripheral surface of the side cover and having one end thereof screw-coupled to the second hole of the first holder; a locking means into which a rod is inserted so as to be movable in an axial direction at a predetermined distance across the second hole of the first holder and the third hole of the second holder.

Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: A display device is provided. The display device includes a display panel and an upper container in which the display panel is disposed. The upper container includes a cover portion which covers top edges of the display panel, a side wall which extends from the cover portion to cover a side of the display panel, and apertures defined in the side wall of the upper container, the apertures exposing the display panel to outside the display device at the side wall.