Abstract: A pixel circuit, a method for driving the same, a display panel and a display apparatus, the pixel circuit includes: a light-emitting device; a driving transistor coupled to the light-emitting device; a first control circuit coupled to a gate of the driving transistor; a second control circuit coupled to a first setting electrode of the driving transistor and configured to initialize the first setting electrode of the driving transistor before the light-emitting device is driven to emit light; a third control circuit coupled to the driving transistor and configured to reset the gate of the driving transistor, control the data voltage to be input into the gate of the driving transistor, and control the driving transistor to generate an operating current according to a data voltage to drive the light-emitting device to emit light.

Abstract: A pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit, and a first control sub-circuit. The data writing sub-circuit is configured to write a data signal provided by a data line into a second node under control of a first scan line. The compensation sub-circuit is configured to write a threshold voltage of the driving sub-circuit into the first node under control of a second scan line. The first control sub-circuit is configured to provide a reference voltage signal provided by a reference voltage line to the second node under control of the first control line after the data writing sub-circuit writes the data signal into the second node, so that the data signal written into the second node is coupled to the first node through the storage sub-circuit.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a base substrate, and a compensation signal line and a plurality of sub-pixels on the base substrate. The sub-pixel includes a sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor and a compensation structure. The compensation structure is coupled to the corresponding compensation signal line. An orthographic projection of the compensation structure onto the base substrate is located at a side of an orthographic projection of a gate electrode of the driving transistor onto the base substrate.

Abstract: Disclosed are a display panel and a display device. The pixel circuit in the display panel includes a control circuit, a drive circuit, and a regulating circuit. The control circuit controls the potential of the coupled control node based on the gate drive signal provided by the gate line and the data signal provided by the data line. The drive circuit drives the light-emitting element to emit light based on the potential of the control node and the drive power signal provided by the drive power line. The regulating circuit adjusts the potential of the control node through the coupling effect based on the drive power signal and the initial power signal provided by the initial power line.

Abstract: In a pixel circuit, a first reset transistor is coupled between a gate of a drive transistor and an initialization signal terminal, and a gate of the first reset transistor is coupled to a reset control terminal; a compensation transistor is coupled between the gate and a first electrode of the drive transistor, and a gate of the compensation transistor is coupled to a first scan control terminal; a data writing transistor is coupled between a second electrode of the drive transistor and a data signal terminal, and a gate of the data writing transistor is coupled to a second scan control terminal; a first light emitting control transistor is coupled between the second electrode of the drive transistor and a first power supply terminal, and a gate of the first light emitting control transistor is coupled to a light emitting control terminal.

Abstract: Provided is a shift register unit. The shift register unit includes: a first input circuit, coupled to a first clock terminal, an input terminal, a first node and a second node; a second input circuit, coupled to the first node, the first clock terminal, a first power terminal and a third node; a first control circuit, coupled to the input terminal, the first clock terminal, the second node, a second power terminal, a second clock terminal and the third node; a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the second power terminal, a fourth node and a fifth node; and an output circuit, coupled to the fourth node, the fifth node, the first power terminal, the second power terminal and an output terminal.

Abstract: An array substrate is provided. The array substrate includes a plurality of data lines; a plurality of second fanout connecting lines; and a plurality of first voltage supply lines. In at least one subpixel of the array substrate, an individual data line of the plurality of data lines and an individual second fanout connecting line of the plurality of second fanout connecting lines have a substantial mirror symmetry with respect to an individual first voltage supply fine of the plurality of first voltage supply lines.

Abstract: Provided is a display substrate, including a base substrate and a plurality of pixel units, the plurality of pixel units includes regular pixel units and redundant pixel units, each regular pixel unit includes at least one constant voltage terminal and at least one dual-gate transistor, each dual-gate transistor includes two gates which are spaced apart, and a part of an active region of the dual-gate transistor, which is located between the two gates, is an intermediate part; the display substrate further includes a plurality of compensation structures, each compensation structure is connected to one constant voltage terminal of the pixel unit, and compensates for the at least one dual-gate transistor of a regular pixel unit; the compensation structure overlaps and is insulated from the intermediate part of the dual-gate transistor for which the compensation structure compensates.

Abstract: Disclosed is a pixel drive circuit which is configured to drive a light emitting element to emit light and includes: a node control sub-circuit, configured to provide a signal of an initial signal terminal to a first node under control of a reset signal terminal, provide a signal of a second node to the first node under control of a scan signal terminal, and adjust a signal of the first node or the second node under control of a first control terminal; a drive sub-circuit, configured to provide a drive current to the second node under control of the first node and the third node; and a light emitting control sub-circuit, configured to provide a signal of a first power terminal to the third node and a signal of the second node to the fourth node under control of a light emitting control terminal.

Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a driving transistor; a storage capacitor having a first capacitor electrode and a second capacitor electrode; a coupling capacitor having a third capacitor electrode and a fourth capacitor electrode; a control transistor; and a data write transistor having a gate electrode connected to a gate line, a first electrode connected to a data line, and a second electrode connected to a first electrode of the control transistor; wherein the control transistor has a gate electrode connected to a fourth control signal line, a first electrode connected to the second electrode of the data write transistor, and a second electrode connected to the first capacitor electrode and the fourth capacitor electrode; a gate electrode of the driving transistor is connected to the third capacitor electrode; and the control transistor is an n-type transistor.

Abstract: A pixel driving circuit, a method for driving the same and a display apparatus. The pixel driving circuit includes: a light-emitting device; a driving transistor which generates a current for driving the light-emitting device to emit light according to a data voltage; a first control circuit which conducts a first electrode of the driving transistor to a first node; a second control circuit which forms a current path from the first node to a first initialization signal terminal in a case where the first control circuit conducts the first electrode of the driving transistor to the first node, to allow a threshold voltage of the driving transistor to be input to the first node; a data writing circuit which inputs the data voltage of a data signal terminal to the first node.

Abstract: A display panel and a display apparatus are disclosed. The display panel includes: a display region, including M first display regions sequentially disposed along a first direction, and a non-display region, including M first GOA circuits and M clock signal line groups; a first display region includes multiple first signal lines sequentially disposed along the first direction and extending along a second direction intersecting with the first direction, a clock signal line group includes multiple clock signal lines, signals of at least two clock signal lines respectively in at least two clock signal line groups are same; a first GOA circuit includes multiple first GOA units, multiple first GOA units in an m-th first GOA circuit are connected with at least one clock signal line in an m-th clock signal line group, and are connected with multiple first signal lines in an m-th first display region in one-to-one correspondence.

Abstract: Provided is a shift register unit. The shift register unit includes: a first input circuit, coupled to a first clock terminal, an input terminal, a first node and a second node; a second input circuit, coupled to the first node, the first clock terminal, a first power terminal and a third node; a first control circuit, coupled to the input terminal, the first clock terminal, the second node, a second power terminal, a second clock terminal and the third node; a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the second power terminal, a fourth node and a fifth node; and an output circuit, coupled to the fourth node, the fifth node, the first power terminal, the second power terminal and an output terminal.

Abstract: A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels arranged on the base substrate. A plurality of sub-pixel driving circuitries in the plurality of sub-pixels is arranged in columns, the columns of sub-pixel driving circuitries are divided into a plurality of column units, and each column unit includes at least two adjacent columns of sub-pixel driving circuitries. The display substrate further includes a first initialization signal transmission layer including a first initialization bus and a plurality of first initialization branches. The first initialization branch includes a first branch body member and a plurality of first branch extending members. The first branch body member is coupled to the sub-pixel driving circuitries in a corresponding column unit through the plurality of first branch extending members.

Abstract: A pixel driving circuit includes: a driving circuit, connecting a first node, a second node, and a third node, and configured to provide a driving current to the third node by using the second node; a compensation circuit, connecting the third node, a fourth node, and a first gate driving signal end, and configured to conduct the third node and the fourth node; a first reset circuit, connecting a first initial signal end, a fifth node, and a first reset signal end, and configured to transmit a signal of the first initial signal end to the fifth node; a first isolation circuit, connecting the first node and the fourth node, and configured to conduct the first node and the fourth node; and a second isolation circuit, connecting the first node and the fifth node, and configured to conduct the first node and the fifth node.

Abstract: A pixel driving circuit and a driving method therefor, and a display panel and a display apparatus. The pixel driving circuit comprises a write-in transistor, a driving transistor, a storage capacitor, a coupling capacitor and a light-emitting unit, wherein one electrode of the storage capacitor and a gate electrode of the driving transistor are both electrically connected to a first node; and one electrode of the coupling capacitor is electrically connected to a control voltage end, and the other electrode thereof is electrically connected to the first node, and the coupling capacitor is configured to adjust the voltage of the first node in a light emission phase, such that the voltage of the first node is converted from a first voltage into a second voltage.

Abstract: Provided is a display substrate, including a base substrate and a plurality of pixel units, the plurality of pixel units includes regular pixel units and redundant pixel units, each regular pixel unit includes at least one constant voltage terminal and at least one dual-gate transistor, each dual-gate transistor includes two gates which are spaced apart, and a part of an active region of the dual-gate transistor, which is located between the two gates, is an intermediate part; the display substrate further includes a plurality of compensation structures, each compensation structure is connected to one constant voltage terminal of the pixel unit, and compensates for the at least one dual-gate transistor of a regular pixel unit; the compensation structure overlaps and is insulated from the intermediate part of the dual-gate transistor for which the compensation structure compensates.

Abstract: The present disclosure provides a timing controller applied to a display device, where the display device includes a plurality of pixel circuits, a first driving circuit and a second driving circuit, each of the pixel circuits includes a driving transistor and a writing and compensation circuit; the first driving circuit is configured to sequentially output a first effective level signal to each of first control signal lines, according to a first driving start signal; the second driving circuit is configured to sequentially output a second effective level signal to each of second control signal lines, according to a second driving start signal; and the timing controller is configured to provide the first driving start signal and the second driving start signal during a refresh frame, where the number W of effective pulses in the first driving start signal is more than or equal to 2.

Abstract: The present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a flexible substrate, and a TFT driver circuit on the flexible substrate. The TFT driver circuit includes a patterned semiconductor layer on the flexible substrate. The display substrate further includes a shielding layer configured to shield fluoride ions from entering the flexible substrate. The shielding layer is arranged at a same layer as the semiconductor layer, and/or the shielding layer is located between the semiconductor layer and the flexible substrate.

Abstract: A display substrate includes pixel circuits and light-emitting devices. The pixel circuits include first pixel circuits and second pixel circuits. The light-emitting devices include first light-emitting devices and second light-emitting devices. A first pixel circuit is coupled to a first light-emitting device, and the first pixel circuit is at least partially opposite to the first light-emitting device. A second pixel circuit is coupled to a second light-emitting device, and an orthographic projection of the second pixel circuit and an orthographic projection of the second light-emitting device have no overlap. A width-to-length ratio of a channel of a driving transistor in the first pixel circuit is greater than a width-to-length ratio of a channel of a driving transistor in the second pixel circuit; and/or a channel capacitance of a compensation transistor in the first pixel circuit is larger than a channel capacitance of a compensation transistor in the second pixel circuit.