Abstract: A display unit, a splicing screen, and a display device are provided. The display unit includes an edge area, and the edge area includes a mounting area and a side binding area. The display unit further includes: a first driving circuit layer located in the edge area and disposed on a side of the base substrate, a plurality of micro light-emitting elements disposed on the first driving circuit layer, and a binding part disposed in the side binding area and connected to the first driving circuit layer.

Abstract: A spliced panel is disclosed. At least two display panels are spliced to each other. Each of the at least two display panels includes a bending part and a non-bending part. The bending part is bent from a side of the non-bending part to a back surface of the at least two display panels. The non-bending part is configured to display an image. In the at least two display panels spliced to each other, the bending part of one of the at least two display panels is correspondingly spliced to the bending part of another of the at least two display panels to form a support structure. A light-emitting diode (LED) substrate is disposed on the support structure.

Abstract: A spliced screen and a display device are provided. A light-emitting unit is arranged and covers the area between display areas of a two unit screens. When the display area of the unit screens normally functions, a plurality of light-emitting units on a light bar can be transmitted and displayed synchronously, cover an area which cannot be shown between the display areas of the two unit screens, and further, weaken or eliminate a slit visually. In this way, the display screen of each of the unit screens is coherently connected to the display screen, and the visual screen-to-body ratio increases as well.

Abstract: A spliced display panel and a spliced display device are provided. At least two display panels are spliced to form a gap. The light-emitting diode substrate is disposed between two adjacent display panels. The first supporting portion of the light-emitting diode substrate is disposed on one of the display panels, and the second supporting portion of the light-emitting diode substrate is disposed on another one of the display panels. The carry portion is disposed on the first supporting portion and the second supporting portion to shield the gap.

Abstract: The present application provides a splicing display device, a light-emitting diode (LED) substrate is arranged on adjacent display devices, and the LED substrate covers a gap. LED elements are arranged on a base. A first magnetic member is arranged on the base. A fastening module includes a fastening element and a magnetic assembly. The fastening element is arranged on a support module. At least a portion of the fastening element is arranged corresponding to the gap. The magnetic assembly is arranged on the fastening element and located in the gap. The magnetic assembly is magnetically connected to the first magnetic member.

Abstract: The present application provides a splicing display device, a light-emitting diode (LED) substrate is arranged on adjacent display devices, and the LED substrate covers a gap. LED elements are arranged on a base. A first magnetic member is arranged on the base. A fastening module includes a fastening element and a magnetic assembly. The fastening element is arranged on a support module. At least a portion of the fastening element is arranged corresponding to the gap. The magnetic assembly is arranged on the fastening element and located in the gap. The magnetic assembly is magnetically connected to the first magnetic member.

Abstract: A low power hybrid reverse (LPHR) bandgap reference (BGR) and digital temperature sensor (DTS) or a digital thermometer, which utilizes subthreshold metal oxide semiconductor (MOS) transistor and the PNP parasitic Bi-polar Junction Transistor (BJT) device to form a reverse BGR that serves as the base for configurable BGR or DTS operating modes. The LPHR architecture uses low-cost MOS transistors and the standard parasitic PNP device. Based on a reverse bandgap voltage, the LPHR can work as a configurable BGR. By comparing the configurable BGR with the scaled base-emitter voltage, the circuit can also perform as a DTS with a linear transfer function with single-temperature trim for high accuracy.

Abstract: A frequency doubler (tripler, or quadrupler) employs current re-use coupled oscillator technique to enhance phase noise without increasing current consumption. Frequency doubler uses coupling between two oscillators running at different frequencies; a first oscillator is running at the target frequency and a second oscillator is running at half the frequency. The coupling between the two oscillators is via a transformer having a primary transformer coil and a secondary transformer coil. The first oscillator comprises a differential inductor, coarse/fine tuning capacitor arrays, and an n-type trans-conductor (GM). A virtual ground node of the n-type GM is coupled to one side of the primary transformer coil and the other side of the primary coil is coupled to the center tap of the secondary coil. The second oscillator comprises the secondary coil, coarse/fine tuning capacitor arrays, n-type GM, frequency tracking loop (FTL) and 2nd-harmonic LC filter network.

Abstract: A frequency doubler (tripler, or quadrupler) employs current re-use coupled oscillator technique to enhance phase noise without increasing current consumption. Frequency doubler uses coupling between two oscillators running at different frequencies; a first oscillator is running at the target frequency and a second oscillator is running at half the frequency. The coupling between the two oscillators is via a transformer having a primary transformer coil and a secondary transformer coil. The first oscillator comprises a differential inductor, coarse/fine tuning capacitor arrays, and an n-type trans-conductor (GM). A virtual ground node of the n-type GM is coupled to one side of the primary transformer coil and the other side of the primary coil is coupled to the center tap of the secondary coil. The second oscillator comprises the secondary coil, coarse/fine tuning capacitor arrays, n-type GM, frequency tracking loop (FTL) and 2nd-harmonic LC filter network.

Abstract: Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.

Abstract: Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.

Abstract: An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.

Abstract: An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.

Abstract: Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

Abstract: Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

Abstract: In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

Abstract: Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

Abstract: In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

Abstract: In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.

Abstract: A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature compensation circuit configured to receive the sense voltage and produce a temperature compensation control signal to control a compensation capacitor array of an oscillator. The temperature compensation circuit may be configured to calibrate the control signal to have a first value at a first temperature. The temperature compensation circuit may also be configured to calibrate a trimming level (e.g., slope) of the control signal.