Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase.

Abstract: A data interface sleep and wakeup method includes receiving data information sent by a second electronic device, where the data information includes sleep information, and setting, based on the sleep information, at least one data interface to either a sleep state or a wakeup state.

Abstract: Embodiments of this application disclose an encoding method and a related device. The method includes: receiving a to-be-encoded code block whose length is L, where L is a positive integer; and encoding the to-be-encoded code block to obtain a forward error correction FEC code, where a valid information length K of the FEC code is an integer multiple of a largest prime factor of L, and a total length N of the FEC code is a sum of K and a product of 2 and an error correction capability T of the FEC code. According to the embodiments of this application, it can be ensured that an FEC codeword satisfies a requirement for a low latency and a high gain.

Abstract: A flat-plate heat pipe and a preparation method thereof, and a heat exchanger are provided. The flat-plate heat pipe includes an upper shell (11) and a lower shell (12); the upper shell (11) and the lower shell (12) are assembled with each other to form a flat-plate shell (10) with a sealed cavity; the sealed cavity is filled with a phase change working medium; a capillary wick (20) is arranged in the flat-plate shell (10); and a surface of the capillary wick (20) has a micro-nano structure. By means of the arrangement of the above capillary wick having the micro-nano structure on the surface thereof, the flat-plate heat pipe has excellent heat conductivity and high resistance to gravity, and is flexible in use and arrangement.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: This application provides an electronic module and an electronic device. The electronic module includes a first component, a second component, and a plurality of terminals. The first component includes a package substrate and a chip mounted on the package substrate. The second component includes a circuit board and a mount base mounted on the circuit board. Each terminal includes a body part, and a first bent part and a solder ball that are respectively connected to two opposite ends of the body part. In each terminal, the body part passes through and is fastened to the mount base, the first bent part presses against a corresponding first solder pad on the package substrate, and the solder ball is connected to a corresponding second solder pad on the circuit board.

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: This application provides a method for detecting margins of a data signal. A receive end of a data signal may adjust a voltage of a reference power source; adjust, based on a plurality of reference moments included in a reference moment set, a moment of an edge of a data strobe signal transmitted by a transmit end of the data signal; and during the adjustment, for each reference voltage and each reference moment, determine whether a bit error exists in data obtained by decoding the data signal when the voltage of the reference power source is the reference voltage and the moment of the edge of the data strobe signal is the reference moment, to obtain a timing margin of the data signal at each reference voltage and a voltage margin of the data signal at each reference moment.

Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

Abstract: A communication method is applicable to a processing apparatus that includes a processor and a communications interface. The processor determines a first parameter corresponding to the communications interface, wherein the communications interface is connected to at least one storage apparatus and communicates with the at least one storage apparatus based on the first parameter. In this way, the processor determines a parameter used to improve a quality of signal transmission and integrity during communication between the processing apparatus and the at least one storage apparatus.

Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

Abstract: A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.

Abstract: A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.

Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: Embodiments of this application disclose an encoding method and a related device. The method includes: receiving a to-be-encoded code block whose length is L, where L is a positive integer; and encoding the to-be-encoded code block to obtain a forward error correction FEC code, where a valid information length K of the FEC code is an integer multiple of a largest prime factor of L, and a total length N of the FEC code is a sum of K and a product of 2 and an error correction capability T of the FEC code. According to the embodiments of this application, it can be ensured that an FEC codeword satisfies a requirement for a low latency and a high gain.

Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

Abstract: A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.