Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Abstract: A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

Abstract: A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.

Abstract: A method, an apparatus, and a communication node for suppressing output noises of peripheral component interconnect express (PCIe) devices in optical fiber communication is provided. The communication node includes a PCIe chip and a detection and control circuit connected to a transmitting end of the PCIe chip. The PCIe chip transmits an electrical signal by a transmitter of a first lane. The detection and control circuit detects a differential-mode voltage of the electrical signal. If the differential-mode voltage is lower than a first threshold, the detection and control circuit controls an optical module connected to the PCIe chip not to transmit an optical signal through the first lane of the optical module. When a PCIe system includes the communication node, output noises of the transmitter is suppressed, and a normal optical fiber communication link is ensured.

Abstract: A method, an apparatus, and a communication node for suppressing output noises of peripheral component interconnect express (PCIe) devices in optical fiber communication is provided. The communication node includes a PCIe chip and a detection and control circuit connected to a transmitting end of the PCIe chip. The PCIe chip transmits an electrical signal by a transmitter of a first lane. The detection and control circuit detects a differential-mode voltage of the electrical signal. If the differential-mode voltage is lower than a first threshold, the detection and control circuit controls an optical module connected to the PCIe chip not to transmit an optical signal through the first lane of the optical module. When a PCIe system includes the communication node, output noises of the transmitter is suppressed, and a normal optical fiber communication link is ensured.