Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.

Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure over a substrate defining a cell area and a peripheral area and having a source region, the stacked structure including interlayer dielectric layers and sacrifice layers, forming channel layers connected to the substrate through the stacked structure of the cell area, forming a first slit in the stacked structure of the cell area, forming a second slit in the stacked structure, the second slit including a first portion and a second portion, removing the sacrifice layers exposed through the first and second slits, forming conductive layers to fill spaces from which the sacrifice layers are removed, forming an insulating layer in the second slit, and forming a source contact by burying a conductive material in the first portion of the second slit having the insulating layer formed therein.

Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.

Abstract: A semiconductor memory device and a method of operating the same are provided. The method includes performing an overall erase operation such that each threshold voltage of all memory cells connected to even word lines and odd word lines in a selected memory cell block are lower than a first target level, performing an erase operation such that each threshold voltage of the memory cells connected to the even word lines are lower than a second target level which is lower than the first target level, and performing an erase operation such that each threshold voltage of the memory cells connected to the odd word lines are lower than the second target level.

Abstract: A semiconductor memory device includes a memory cell array including first memory cells and second memory cells connected to at least one word line, a circuit group configured to perform a pre-program operation on the first memory cells using a target voltage and a main program operation on the first memory cells and the second memory cells using a final target voltage, and a control circuit configured to set the target voltage depending on variations in threshold voltages of the first memory cells caused by the main program operation of the second memory cells.

Abstract: A non-volatile memory device includes a first string and a second string that each include a first drain selection transistor, a second drain selection transistor, a plurality of memory cells, and a source selection transistor that are coupled in series in that order, respectively, a first bit line coupled with a node between the first and second drain selection transistors of the first string, and a second bit line coupled with an end node of the second string on the side of the first drain selection transistor of the second string, wherein gates of the first drain selection transistors of the first and second strings are coupled with each other, and gates of the second drain selection transistors of the first and second strings are coupled with each other.

Abstract: A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.