Patents by Inventor Yoojin Kim

Yoojin Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220024815
    Abstract: An electronic device according to various embodiments of the disclosure may include a housing including a first plate forming an outer face. The first plate may include a glass plate including a first surface outwardly facing the housing and a second surface inwardly facing the housing, a coating layer including an anti-reflection coating and/or an anti-finger coating above the first surface while forming the outer face, a first layer formed between the first surface of the first glass plate and the coating layer, having a first thickness, and including a first inorganic material, a second layer formed between the first layer and the coating layer, having a second thickness, and including a second inorganic material different from the first inorganic material, a third layer formed between the second layer and the coating layer, having a third thickness thicker than each of the first thickness and the second thickness, and including a third inorganic material, and an opaque layer formed on the second surface.
    Type: Application
    Filed: December 3, 2019
    Publication date: January 27, 2022
    Inventors: Sejin KIM, Jinchoul PARK, Junsang PARK, Wanju SHIN, Hwanju JEON, Younggoo KANG, Yoojin KIM, Gijea PARK, Yunhui CHO
  • Publication number: 20210174178
    Abstract: A method of processing data includes manipulating input data based on a configuration of the input data and a configuration of hardware for processing the input data to generate manipulated data; rearranging the manipulated data based on sparsity of the manipulated data to generate rearranged data; and processing the rearranged data to generate output data.
    Type: Application
    Filed: June 9, 2020
    Publication date: June 10, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyunsun PARK, Yoojin KIM, Junwoo JANG
  • Publication number: 20210117781
    Abstract: A processor-implemented neural network method includes: generating a bit vector based on whether each of a plurality of input activations within a neural network is 0; merging the bit vector into the input activations such that bit values within the neural network included in the bit vector are most significant bits (MSBs) of multi bit expressions of the input activations; merging the bit vector into weights such that the bit values included in the bit vector are MSBs of multi bit expressions of the weights; sorting the input activations and the weights based on bits corresponding to the MSBs; and implementing the neural network, including performing operations between the sorted input activations and the sorted weights.
    Type: Application
    Filed: April 24, 2020
    Publication date: April 22, 2021
    Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Yoojin KIM, Soonhoi HA, Donghyun KANG, Jintaek KANG
  • Publication number: 20210064992
    Abstract: A method of processing data includes identifying a sparsity of input data, based on valid information included in the input data, rearranging the input data, based on a form of the sparsity, and generating output data by processing the rearranged input data.
    Type: Application
    Filed: February 27, 2020
    Publication date: March 4, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyunsun PARK, Yoojin KIM, Hyeongseok YU, Sehwan LEE, Junwoo JANG
  • Publication number: 20200221589
    Abstract: An electronic device includes a housing including a first plate, a second plate facing away from the first plate, and a lateral member surrounding a space between the first plate and the second plate; a display visible through at least part of the first plate; and a glass construction constructing at least part of the second plate. The glass construction includes a glass plate including a first face outwardly facing the housing and a second face facing away from the first face, an inorganic layer including a first roughness and constructed on the first face, a first polymer layer disposed between the first plate and the second face, an Optically Clear Adhesive (OCA) layer disposed between the second face and the first polymer layer, and a second polymer layer disposed between the first plate and the first polymer layer and including a third face and a fourth face.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 9, 2020
    Inventors: Soonho HAN, Yoojin KIM, Hyunggon LEE, Jongchul CHOI
  • Publication number: 20200198294
    Abstract: An electronic device including a housing, a display, an adhesive layer, a first decoration layer, and a second decoration layer. The housing includes a front plate, a rear plate, and a lateral member surrounding a space between the front and rear plates. The display is viewed through at least a portion of the front plate. The adhesive layer is combined with one of the front and rear plates. The first decoration layer includes a first shape-cured layer and a first color layer. The first shape-cured layer is combined with the adhesive layer, has a first three-dimensional pattern, and is cured by an external stimulus. The second decoration layer includes a second shape-cured layer and a second color layer. The second shape-cured layer is combined with the first color layer, has a second three-dimensional pattern, and is cured by an external stimulus.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Hyunggon LEE, Soonwoo KWON, Yoojin KIM, Saehee LEE, Yunhui CHO
  • Patent number: 7785753
    Abstract: Disclosed is a method for processing a two layer mask for use in fabrication of semiconductor devices whereby the critical dimension (CD) of a semiconductor device being fabricated with the mask can be controlled. After forming a carbon mask layer and a silicon containing photoresist layer on the carbon mask, a two-step process forms openings in the carbon mask layer, as required for subsequent device fabrication. The structure is placed in a plasma processing chamber, and an oxygen plasma is employed to partially etch the carbon layer. The oxygen plasma reacts with silicon in the photoresist to form a hard silicon oxide layer on the surface of the photoresist. A hydrogen plasma is then employed to complete the etch through the carbon layer with a reduced critical dimension. Damage to the silicon containing photoresist layer is kept to a minimum during the plasma etch process by limiting the low frequency RF power.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: August 31, 2010
    Assignee: Lam Research Corporation
    Inventors: Yoojin Kim, Camelia Rusu, Jonathan Kim
  • Publication number: 20070269721
    Abstract: Disclosed is a method for processing a two layer mask for use in fabrication of semiconductor devices whereby the critical dimension (CD) of a semiconductor device being fabricated with the mask can be controlled. After forming a carbon mask layer and a silicon containing photoresist layer on the carbon mask, a two-step process forms openings in the carbon mask layer, as required for subsequent device fabrication. The structure is placed in a plasma processing chamber, and an oxygen plasma is employed to partially etch the carbon layer. The oxygen plasma reacts with silicon in the photoresist to form a hard silicon oxide layer on the surface of the photoresist. A hydrogen plasma is then employed to complete the etch through the carbon layer with a reduced critical dimension. Damage to the silicon containing photoresist layer is kept to a minimum during the plasma etch process by limiting the low frequency RF power.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 22, 2007
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Yoojin Kim, Camelia Rusu, Jonathan Kim