Patents by Inventor Yoon Cho

Yoon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250097665
    Abstract: A chatting service method and apparatus is disclosed. A method of operating a server providing a chatting service corresponding to one or more themes, according to an embodiment, may include: receiving a message including area information through a chat room corresponding to a specific theme; providing a map interface for exposing information about the message to a terminal; determining an area range based on view manipulation information of the map interface received from the terminal; extracting message information corresponding to the area range; and providing the extracted message information through the map interface.
    Type: Application
    Filed: September 17, 2024
    Publication date: March 20, 2025
    Inventors: Soo Yeun JANG, Su Min CHO, Hae Yoon CHO, Maria PARK
  • Patent number: 12211581
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: January 28, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Patent number: 12195583
    Abstract: A biodegradable resin composition is obtained by subjecting an aliphatic dicarboxylic acid or an acid component comprising a mixture of an aliphatic dicarboxylic acid and an aromatic dicarboxylic acid, and an aliphatic diol sequentially to esterification, transesterification, polycondensation, chain extension and solid-state polymerization reactions in the presence of a polyfunctional compound represented by the following Formula 1: wherein n is an integer ranging from 1 to 11, and m is an integer ranging from 2 to 30.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: January 14, 2025
    Assignee: ANKOR BIOPLASTICS CO., LTD.
    Inventors: Heon Young Lim, Yoon Cho, Myung Je You
  • Patent number: 12112827
    Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 8, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Hwan Kim, Jun Young Park, Jin Do Byun, Kwang Seob Shin, Eun Seok Shin, Hyun-Yoon Cho, Young Don Choi, Jung Hwan Choi
  • Publication number: 20240212746
    Abstract: Disclosed is a memory device which includes a pull-up driver that is connected between a power supply voltage and a first node, a T-coil circuit that is connected between the first node and a second node, an external resistor, and a ZQ controller that performs a ZQ calibration operation on the pull-up driver. The ZQ controller includes a path selecting circuit that selects one node among the first node and the second node, a comparing circuit that compares a voltage of the one node selected by the path selecting circuit with a pull-up reference voltage and outputs a comparison result, and a code generating circuit that generates a pull-up code for driving the pull-up driver, based on the comparison result. While the pull-up code is generated, the external resistor is connected between the second node and a ground voltage.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 27, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsu JUNG, Jindo BYUN, Joohwan KIM, Eun Seok SHIN, Hyun-Yoon CHO, Junghwan CHOI
  • Publication number: 20240177250
    Abstract: A computer-implemented method of managing the productivity of fish in a land-based aquafarm through data prediction for each growth period is proposed. The method may include predicting, at a processor, a feed amount input to an aquaculture tank based on aquaculture tank sensing data. The method may also include predicting, at the processor, the growth of fish based on results of the prediction of the input feed amount.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 30, 2024
    Inventors: Sung Yoon CHO, Ki Won KWON, Won Gi JEON, Yang Seob KIM, Juhyoung SUNG, Da Eun JUNG, Young Myoung KO, Jongwon KIM, Eunbi PARK
  • Patent number: 11930468
    Abstract: A wireless communication method includes: receiving a wireless signal including a plurality of frames, wherein each of the plurality of frames includes a plurality of sub-frames and a current frame is initially a first one of the frames; a) performing a correlation calculation between each of the sub-frames of the current frame and each a plurality of reference signals to generate a plurality of current correlation values; b) respectively accumulating the current correlation values with previous correlation values to generate cumulative values respectively corresponding to the plurality of sub-frames of the current frame; determining whether an effective synchronization signal is detected, based on the current cumulative values; and setting the current frame to a next one of the frames, setting the previous correlational values to the current correlation values, and determining whether to resume to step a) based on the determination as to whether the effective synchronization signal is detected.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-Chul Lee, Sung-Yoon Cho
  • Publication number: 20230360689
    Abstract: A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.
    Type: Application
    Filed: April 26, 2023
    Publication date: November 9, 2023
    Inventors: Jun Young Park, Joo Hwan Kim, Jin Do Byun, Eun Seok Shin, Hyun Sub Rie, Hyun-Yoon Cho, Jung Hwan Choi
  • Patent number: 11795268
    Abstract: A functional resin composition comprising a biomass-derived component; an aromatic dicarboxylic acid; an alcohol component; a chain extender; and a multifunctional compound. The biomass-derived component is biomass-derived succinic acid or mixture with fossil-derived aliphatic dicarboxylic acid. The multifunctional compound is obtained by reaction of 4,4-bis(4-hydroxyphenyl)valeric acid and polyethylene glycol. The functional resin composition has excellent processability, moldability, tearing strength, tensile strength and excellent resistance to hydrolysis.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 24, 2023
    Assignee: ANKOR BIOPLASTICS CO., LTD.
    Inventors: Heon-Young Lim, Seung-Lyul Choi, Yoon Cho
  • Publication number: 20230299433
    Abstract: Provided is a method for welding an electrode assembly comprising stacking a plurality of electrodes to manufacture the electrode assembly, attaching a buffer tab to a surface of an outermost electrode tab of the electrode assembly, and welding a lead such that a plurality of electrode tabs and the lead are in contact with each other to dispose the buffer tab therebetween. The electrode assembly comprises the stacked plurality of electrodes comprising the lead welded to the plurality of electrode tabs, and each electrode tab of the plurality of electrode tabs protrudes in one direction from the plurality of electrodes. The buffer tab may be attached, before the welding, to the surface of the outermost electrode tab to minimize or prevent damage to the electrode tab due to pressure applied by a welding rod.
    Type: Application
    Filed: April 19, 2022
    Publication date: September 21, 2023
    Applicant: LG Energy Solution, Ltd.
    Inventors: Hee Yoon Cho, Young Seok Baek
  • Publication number: 20230280782
    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Inventors: Junyoung PARK, YOUNG-HOON SON, HYUN-YOON CHO, YOUNGDON CHOI, JUNGHWAN CHOI
  • Patent number: 11687114
    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: June 27, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyoung Park, Young-Hoon Son, Hyun-Yoon Cho, Youngdon Choi, Junghwan Choi
  • Publication number: 20230143365
    Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.
    Type: Application
    Filed: June 29, 2022
    Publication date: May 11, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joo Hwan KIM, Jun Young PARK, Jin Do BYUN, Kwang Seob SHIN, Eun Seok SHIN, Hyun-Yoon CHO, Young Don CHOI, Jung Hwan CHOI
  • Publication number: 20230066632
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 2, 2023
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Publication number: 20230032384
    Abstract: Provided is a cooling device with which it is possible to cool a fluid to be cooled, even before maintenance work, if a fault such as a blockage or a breakage occurs in a part of a channel. The cooling device (1) is provided with four heat exchangers (1A-1D) and a plurality of heat exchanger connection parts (111-120), each of the heat exchanger connection parts allowing natural gas to flow therethrough. Each of the heat exchangers has: a drum (101, 102, 103, fourth drum 104), a refrigerant reservoir (T), a plurality of heat exchanger core parts (121, 122, 123, 124) immersed in liquid propane in the refrigerant reservoir (T), and a demister (106). A plurality of cooling channels allowing natural gas to flow therethrough are installed, independent of each other, from the first heat exchanger (1A) to the fourth heat exchanger (1D).
    Type: Application
    Filed: May 15, 2020
    Publication date: February 2, 2023
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)
    Inventors: Kenichiro MITSUHASHI, Yasuhiro MITARAI, Jong Yoon CHO
  • Patent number: 11508420
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Patent number: 11461176
    Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Young Park, Young-Hoon Son, Hyun-Yoon Cho, Young Don Choi, Jung Hwan Choi
  • Publication number: 20220243005
    Abstract: The present invention relates to a biodegradable resin composition having improved mechanical properties, formability and weatherproof, and a method for manufacturing the biodegradable resin composition. More specifically, the biodegradable resin composition according to the present invention is obtained by mixing an aliphatic dicarboxylic acid or an acid component comprising a mixture of an aliphatic dicarboxylic acid and an aromatic dicarboxylic acid, and aliphatic diol, and subjecting the mixture sequentially to esterification, transesterification, polycondensation, chain extension and solid-state polymerization reactions in the presence of a polyfunctional compound, and may have improved productivity and economic efficiency due to improved reaction rate, excellent tensile strength, elongation rate and processability. In addition, the biodegradable resin composition according to the present invention is environmentally friendly as it is biodegradable in a natural state when buried.
    Type: Application
    Filed: November 23, 2020
    Publication date: August 4, 2022
    Applicant: ANKOR BIOPLASTICSCO.,LTD.
    Inventors: Heon Young LIM, Yoon CHO, Myung Je YOU
  • Publication number: 20220138045
    Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.
    Type: Application
    Filed: August 10, 2021
    Publication date: May 5, 2022
    Inventors: Jun Young PARK, Young-Hoon SON, Hyun-Yoon CHO, Young Don CHOI, Jung Hwan CHOI
  • Publication number: 20220073981
    Abstract: The present invention provides a biomarker for identifying the expression of an inflammatory-response-associated gene that specifically causes a change in expression due to exposure to 2-butanone, which is harmful and found in indoor environments, and an identification method using the same, and particularly an inflammatory-response-associated gene, the expression of which is increased or decreased by exposure to 2-butanone in a human bronchial epithelial cell line model (BEAS-2B), and a method of identifying exposure and predicting an inflammatory response using the same. The biomarker of the present invention includes specific genes selected through RNA sequencing, and thus can be useful in monitoring and determining the exposure to 2-butanone in the environment, and can be utilized as a tool predicting the mechanism of inflammatory response and toxicity caused by exposure to 2-butanone.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 10, 2022
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae Chun RYU, Yoon CHO