Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.

Abstract: A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

Abstract: A thin film transistor array panel including a substrate; a channel region disposed on the substrate and including oxide semiconductor disposed on the substrate; a source electrode and a drain electrode connected to the oxide semiconductor and facing each other at both sides, centered on the oxide semiconductor; an insulating layer disposed on the oxide semiconductor; and a gate electrode disposed on the insulating layer. The drain electrode includes a first drain region and a second drain region; the charge mobility of the first drain region is greater than that of the second drain region, the source electrode includes a first source region and a second source region, and the charge mobility of the first source region is greater than that of the second source region.

Abstract: A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.

Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A thin film transistor includes an oxide semiconductor, in which an oxygen defect content of the oxide semiconductor is no greater than about 0.15 based on an entire oxygen content included in the oxide semiconductor.

Abstract: A thin film transistor substrate includes the following elements: a base substrate, a data line disposed on the base substrate, a source electrode contacting the data line, a drain electrode spaced from the source electrode, a channel disposed between the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a gate insulation pattern disposed on the channel, and a gate electrode disposed on the gate insulation pattern.

Abstract: A switching element includes an active pattern including a channel portion, a source portion connected to the channel portion, and a drain portion connected to the channel portion, the source portion, a gate electrode overlapping the channel portion of the active pattern, a gate insulation layer disposed between the channel portion of the active pattern and the gate electrode, a source electrode disposed on the source portion of the active pattern to make ohmic contact with the source portion, and a drain electrode disposed on the drain portion of the active pattern to make ohmic contact with the drain portion. The drain portion and the channel portion of the active pattern include the same or substantially the same material.

Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

Abstract: A display substrate includes a base substrate, a data line disposed on the base substrate, a gate line crossing the data line, a first insulation layer disposed on the base substrate, an active pattern disposed on the first insulation layer and comprising a channel comprising an oxide semiconductor, a source electrode connected to the channel, and a drain electrode connected to the channel, a second insulation layer disposed on the active pattern, and contacting to the source electrode and the drain electrode, a gate electrode disposed on the second insulation layer, and overlapping with the channel, a passivation layer disposed on the gate electrode and the second insulation layer, and a pixel electrode electrically connected to the drain electrode through a first contact hole formed through the passivation layer and the second insulation layer.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.

Abstract: A thin film transistor substrate including a base substrate; an active pattern disposed on the base substrate and including a source electrode, a drain electrode, and a channel including an oxide semiconductor disposed between the source electrode and the drain electrode; a gate insulation pattern disposed on the active pattern; a gate electrode disposed on the gate insulation pattern and overlapping with the channel; and a light-blocking pattern disposed between the base substrate and the active pattern.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

Abstract: Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.