Abstract: A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Abstract: A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activating bitline equalizing circuits to precharge the bitlines of at least one of the first and second memory block with a bitline precharge voltage, when the memory block is not currently selected for a data operation. The bitline equalizing voltage generator may be configured to recycle the boost voltage that was used to generate a bitline isolation signal or a wordline drive signal.

Abstract: A decay heat removal system for a liquid metal reactor, in which a decay heat exchanger (DHX) is installed concentrically with an intermediate heat-exchanger (IHX) in the same cylinder which separates the DHX and IHX from the reactor pool fluid, and serves to remove the reactor core decay heat. The cylinder surrounds the IHX and the DHX, and has an opened top portion protruded out of the level of the fluid in a hot pool, a bottom portion connected to a cold pool and a guide pipe for allowing the passage of the fluid from the hot pool into the IHX. The decay heat removal system can remove decay heat immediately after occurrence of an accident, thereby improves the safety of a nuclear plant.

Abstract: Provided is a circuit for use in a semiconductor memory optimized to improve data read ability at low supply voltages. Circuit includes a direct sense AMP circuit, an input/output gate circuit, and an operation control unit. The direct sense AMP circuit transmits read data loaded in a bit line pair including first and second bit lines to a data input/output pair including first and second data input/output lines in response to a read command signal. The input/output gate circuit which, in response to a read/write signal, also passes the read data loaded in the bit line pair directly to the data input/output line pair, and passes write data loaded in the data input/output line pair directly to the bit line pair.

Abstract: A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

Abstract: A voltage boosting circuit and a method of generating a boosting voltage alleviate deterioration of a driver transistor caused by high voltage stress when the level of an external supply voltage is high. The voltage boosting circuit includes boosting capacitors and switches. The boosting capacitors include a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage. The switches connect the boosting capacitors in series in response to a control signal. The boosting voltage increases or decreases as the voltage level at the driving node changes according to the logic state of a boosting level control signal. The boosting level control signal is responsive to the external supply voltage level. An external supply voltage detector detects the level of external supply voltage level and generates the boosting level control signal.

Abstract: A semiconductor integrated circuit may include an internal circuit, and a power-on reset circuit for generating a power-on reset signal to initialize the internal circuit at a power-on. At the power-on, the power-on reset circuit delays a transition of the power-on reset signal from a first level to a second level until a given time duration after the power supply voltage reaches a detection voltage.

Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Abstract: A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

Abstract: A high frequency equalizer using a demultiplexing technique and a semiconductor device using the same are provided. The high frequency equalizer demultiplexes input data input through an input and output terminal into a plurality of input data items, each having a time difference that is the same as the period of the input data. The equalizer restores the lost high frequency data components of the plurality of demultiplexed input data items, multiplexes the restored plurality of data items, and sequentially outputs the restored data items one by one. Therefore, using this high frequency equalizer, it is possible to allow enough time to restore the lost high frequency component even though the period of the input data is reduced by an increase of the data transmission speed. Using this high frequency equalizer, it is possible to correctly restore the lost high frequency component even at a high data transmission speed.

Abstract: A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activating bitline equalizing circuits to precharge the bitlines of at least one of the first and second memory block with a bitline precharge voltage, when the memory block is not currently selected for a data operation. The bitline equalizing voltage generator may be configured to recycle the boost voltage that was used to generate a bitline isolation signal or a wordline drive signal.

Abstract: A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

Abstract: A semiconductor integrated circuit may include an internal circuit, and a power-on reset circuit for generating a power-on reset signal to initialize the internal circuit at a power-on. At the power-on, the power-on reset circuit delays a transition of the power-on reset signal from a first level to a second level until a given time duration after the power supply voltage reaches a detection voltage.

Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Abstract: A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

Abstract: Provided is a circuit for use in a semiconductor memory optimized to improve data read ability at low supply voltages. Circuit includes a direct sense AMP circuit, an input/output gate circuit, and an operation control unit. The direct sense AMP circuit transmits read data loaded in a bit line pair including first and second bit lines to a data input/output pair including first and second data input/output lines in response to a read command signal. The input/output gate circuit which, in response to a read/write signal, also passes the read data loaded in the bit line pair directly to the data input/output line pair, and passes write data loaded in the data input/output line pair directly to the bit line pair.

Abstract: Disclosed is a semiconductor memory device which includes an offset-compensated amplifier circuit. The offset-compensated amplifier circuit enables a flip-flop sense amplifier to perform a stable sensing operation irrespective of its own offset voltage. A part of the offset-compensated amplifier circuit is located in a first region (for example, a region that includes the flip-flop sense amplifier), and the other thereof is located in a second region (for example, a region where drivers related to the flip-flop sense amplifier are located). With this distributed arrangement structure, an offset-compensated amplifier circuit can be obtained n the semiconductor memory device.

Abstract: A voltage booster circuit includes first and second capacitors and a switch circuit coupled to the first and second capacitors and operative to apply a power supply across the first and second capacitors in series responsive to a first signal to thereby charge the first and second capacitors and to couple the first and second capacitors in parallel between an output terminal and a power supply node of the power supply responsive to deassertion of the first signal and assertion of a second signal to thereby boost a voltage at the output terminal. The first and second signals may be alternately asserted in a succession of time periods, e.g., the first and second signals may be asserted in respective non-overlapping time periods.

Abstract: A plurality of internal circuits of a memory device are operable at first and second internal voltages, where the first internal voltage is less than the second internal voltage. A first power port of the memory device receives a first power supply voltage, and a second power port of the memory device receives a second power supply voltage, where the first power supply voltage is less than the second power supply voltage. An internal voltage generation circuit of the memory device is selectively operable in either a first mode in which the second internal voltage is generated from the first power supply voltage, or a second mode in which the second internal voltage is generated from the second power supply voltage.