Patents by Inventor Yoon-Joo EOM
Yoon-Joo EOM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071475Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: ApplicationFiled: October 24, 2023Publication date: February 29, 2024Inventors: YOON-JOO EOM, SEUNGJUN BAE, HYE JUNG KWON, YOUNG-JU KIM
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Patent number: 11862234Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: GrantFiled: December 1, 2021Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Seungjun Bae, Hye Jung Kwon, Young-Ju Kim
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Patent number: 11721391Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.Type: GrantFiled: July 28, 2022Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Joon-Young Park, Yongcheol Bae, Won Young Lee, Seongjin Jang, Junghwan Choi, Joosun Choi
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Publication number: 20220366969Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Yoon-Joo EOM, JOON-YOUNG PARK, YONGCHEOL BAE, WON YOUNG LEE, SEONGJIN JANG, JUNGHWAN CHOI, JOOSUN CHOI
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Patent number: 11443794Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.Type: GrantFiled: March 1, 2019Date of Patent: September 13, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Joon-Young Park, Yongcheol Bae, Won Young Lee, Seongjin Jang, Junghwan Choi, Joosun Choi
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Publication number: 20220093161Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Inventors: YOON-JOO EOM, SEUNGJUN BAE, HYE JUNG KWON, YOUNG-JU KIM
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Patent number: 11195571Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: GrantFiled: September 20, 2018Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Seungjun Bae, Hye Jung Kwon, Young-Ju Kim
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Patent number: 10666467Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.Type: GrantFiled: August 22, 2018Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye Jung Kwon, Seungjun Bae, Yongjae Lee, Young-Sik Kim, Young-Ju Kim, Suyeon Doo, Yoon-Joo Eom
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Publication number: 20190272867Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.Type: ApplicationFiled: March 1, 2019Publication date: September 5, 2019Inventors: Yoon-Joo EOM, JOON-YOUNG PARK, YONGCHEOL BAE, WON YOUNG LEE, SEONGJIN JANG, JUNGHWAN CHOI, JOOSUN CHOI
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Patent number: 10361699Abstract: A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.Type: GrantFiled: March 15, 2018Date of Patent: July 23, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Ha Lee, Chang-Kyo Lee, Yoon-Joo Eom
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Publication number: 20190164594Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: ApplicationFiled: September 20, 2018Publication date: May 30, 2019Inventors: YOON-JOO EOM, SEUNGJUN BAE, HYE JUNG KWON, YOUNG-JU KIM
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Publication number: 20190158320Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.Type: ApplicationFiled: August 22, 2018Publication date: May 23, 2019Inventors: Hye Jung Kwon, Seungjun Bae, Yongjae Lee, Young-Sik Kim, Young-Ju Kim, Suyeon Doo, Yoon-Joo Eom
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Patent number: 10255969Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.Type: GrantFiled: July 11, 2018Date of Patent: April 9, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Joon-Young Park, Yongcheol Bae, Won Young Lee, Seongjin Jang, Junghwan Choi, Joosun Choi
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Publication number: 20190052268Abstract: A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.Type: ApplicationFiled: March 15, 2018Publication date: February 14, 2019Inventors: JUN-HA LEE, CHANG-KYO LEE, YOON-JOO EOM
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Publication number: 20180315468Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.Type: ApplicationFiled: July 11, 2018Publication date: November 1, 2018Inventors: Yoon-Joo EOM, JOON-YOUNG PARK, YONGCHEOL BAE, WON YOUNG LEE, SEONGJIN JANG, JUNGHWAN CHOI, JOOSUN CHOI
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Patent number: 10062430Abstract: A multi channel semiconductor device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.Type: GrantFiled: February 6, 2018Date of Patent: August 28, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Joon-Young Park, Yongcheol Bae, Won Young Lee, Seongjin Jang, Junghwan Choi, Joosun Choi
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Publication number: 20180166122Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.Type: ApplicationFiled: February 6, 2018Publication date: June 14, 2018Inventors: Yoon-Joo EOM, JOON-YOUNG PARK, YONGCHEOL BAE, WON YOUNG LEE, SEONGJIN JANG, JUNGHWAN CHOI, JOOSUN CHOI
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Patent number: 9899075Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.Type: GrantFiled: July 9, 2015Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Joon-Young Park, Yongcheol Bae, Won Young Lee, Seongjin Jang, Junghwan Choi, Joosun Choi
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Patent number: 9742355Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.Type: GrantFiled: December 4, 2015Date of Patent: August 22, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Joo Eom, Seung-Jun Bae, Dae-Sik Moon, Joon-Young Park, Min-Su Ahn
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Publication number: 20160164479Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.Type: ApplicationFiled: December 4, 2015Publication date: June 9, 2016Inventors: YOON-JOO EOM, SEUNG-JUN BAE, DAE-SIK MOON, JOON-YOUNG PARK, MIN-SU AHN