Abstract: A flag memory is provided which stores a flag indicating whether or not a corresponding pixel is in the initial state. When writing has been performed on an image memory by a drawing unit, a value of the flag of a corresponding pixel is changed from a first value indicating that the pixel is in the initial state to a second value indicating that the pixel is not in the initial state. When a display unit reads a pixel value from the image memory, a flag corresponding to the pixel is read from the flag memory, and if the flag still has the first value, an initial pixel value is supplied to the display unit, and otherwise, a pixel value read from the image memory is supplied to the display unit.

Abstract: A flag memory is provided which stores a flag indicating whether or not a corresponding pixel is in the initial state. When writing has been performed on an image memory by a drawing unit, a value of the flag of a corresponding pixel is changed from a first value indicating that the pixel is in the initial state to a second value indicating that the pixel is not in the initial state. When a display unit reads a pixel value from the image memory, a flag corresponding to the pixel is read from the flag memory, and if the flag still has the first value, an initial pixel value is supplied to the display unit, and otherwise, a pixel value read from the image memory is supplied to the display unit.

Abstract: A coordinate data read unit reads coordinate data of vertexes of a three-dimensional object stored in a memory into an internal storage unit. A coordinate transformation unit performs coordinate transformation on the coordinate data stored in the internal storage unit. A vertex deletion unit determines whether a piece of the attribute data of each vertex is to be read, based on the transformed pieces of the coordinate data stored in the internal storage unit. An attribute data read unit reads a piece of the attribute data of each vertex determined to be read by the vertex read unit from the memory into the internal storage unit. A display control unit performs drawing processing based on the pieces of the coordinate and the attribute data stored in the internal storage unit.

Abstract: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

Abstract: A processing device performs a geometry process as preprocessing for rendering a three-dimensional object on a display by modeling the three-dimensional object using a polygon mesh. The geometry process includes a vertex process that is performed for each of the vertices of the polygon mesh by a different one of a plurality of processors, and processed vertex data obtained by the vertex process is notified among the processors so that a polygon process can be performed in each of the processors. Because each processor can continuously perform the polygon process immediately after the vertex process, it is possible to suppress the occurrence of the unbalance of timing in performing the vertex process and the polygon process, thereby efficiently performing computation while minimizing the wasteful idle time of the processors.

Abstract: A processing device performs a geometry process as preprocessing for rendering a three-dimensional object on a display by modeling the three-dimensional object using a polygon mesh. The geometry process includes a vertex process that is performed for each of the vertices of the polygon mesh by a different one of a plurality of processors, and processed vertex data obtained by the vertex process is notified among the processors so that a polygon process can be performed in each of the processors. Because each processor can continuously perform the polygon process immediately after the vertex process, it is possible to suppress the occurrence of the unbalance of timing in performing the vertex process and the polygon process, thereby efficiently performing computation while minimizing the wasteful idle time of the processors.

Abstract: A processing device performs a geometry process as preprocessing for rendering a three-dimensional object on a display by modeling the three-dimensional object using a polygon mesh. The geometry process includes a vertex process that is performed for each of the vertices of the polygon mesh by a different one of a plurality of processors, and processed vertex data obtained by the vertex process is notified among the processors so that a polygon process can be performed in each of the processors. Because each processor can continuously perform the polygon process immediately after the vertex process, it is possible to suppress the occurrence of the unbalance of timing in performing the vertex process and the polygon process, thereby efficiently performing computation while minimizing the wasteful idle time of the processors.

Abstract: A device drawing a three-dimensional shape and including a high order bit comparing section comparing high order bits of a depth value retained by a high order Z-buffer memory with high order bits calculated by a calculation section. If these two sets of high order bits are the same, a low order bit comparing section compares low order bits retained by a low order Z-buffer memory with low order bits calculated by the calculation section. If a depth indicated by the high order bits calculated by the calculation section is shallow, the high order bits retained by the high order Z-buffer memory and the low order bits retained by the low order Z-buffer memory are updated. If a depth indicated by the low order bits calculated by the calculation section is shallow, the low order bits retained by the low order Z-buffer memory are updated.

Abstract: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

Abstract: A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads (i) causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and (ii) causes concurrent execution of an operation cell having a configuration for the current thread and an operation cell having a configuration for the next thread.

Abstract: In the case where a previous character (P1) is cleared on a screen (20) and a new character (P2) is displayed on the right of the previous one, first, image data to be transferred (P2) is prepared in a source image memory. Next, a write start address (W) is set at the head of a bit sequence of a left clearance width (LC)×BPP, which precedes the destination address (T) of a frame buffer into which the head (S) of the image data (P2) is to be written. After that, a series of burst transfer repeatedly copies clearance data held in a register into a region of the left clearance width (LC), starting from the write start address (W), and subsequently writes one line (a transfer width (W1)×BPP) of the image data (P2). The write start address is incremented by a frame width (FW)×BPP.

Abstract: A coordinate data read unit (102) reads coordinate data of vertexes of a three-dimensional object stored in a memory (110) into an internal storage unit (106). A coordinate transformation unit (103) performs coordinate transformation on the coordinate data stored in the internal storage unit (106). A vertex deletion unit (104) determines whether a piece of the attribute data of each vertex is to be read, based on the transformed pieces of the coordinate data stored in the internal storage unit (106). An attribute data read unit (105) reads a piece of the attribute data of each vertex determined to be read by the vertex read unit (104) from the memory (110) into the internal storage unit (106). A display control unit (107) performs drawing processing based on the pieces of the coordinate and the attribute data stored in the internal storage unit (106).

Abstract: A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and causes concurrent execution of an operation cell having a configuration for the current thread and (ii) an operation cell having a configuration for the next thread.

Abstract: An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.

Abstract: A processing device for performing a geometry process performed as preprocessing for rendering a three-dimensional object on a display by modeling the three-dimensional object using a polygon mesh. The geometry process includes a vertex process that is performed for each of the vertices of the polygon mesh by a different one of a plurality of processors, and processed vertex data obtained by the vertex process is notified among the processors so that a polygon process can be performed in each of the processors. Since each process or can continuously perform the polygon process immediately after the vertex process, it is possible to suppress the occurrence of the unbalance of timing in performing the vertex process and the polygon process, thereby efficiently performing computation while minimizing the wasteful idle time of the processors.

Abstract: In an image processing apparatus using a read buffer, in a case where access request target data is not stored in the read buffer, the read buffer is controlled such that data corresponding to a position having coordinates, which is most distant from a position having coordinates corresponding to the access request target data, is discarded or replaced. Consequently, the image processing apparatus increases the probability that data corresponding to a position close to a position corresponding to the access request target data remains in the read buffer. Accordingly, the hit rate of the read buffer is increased. Thus, the frequency of access to an external memory can be reduced.

Abstract: An object is to provide a three-dimensional shape drawing device which is capable of drawing a three-dimensional shape at a high speed. A high order bit comparing section compares high order bits of a depth value retained by a high order Z-buffer memory with high order bits of a depth value calculated by a depth value calculation section. If these two sets of high order bits are same, a low order bit comparing section compares low order bits of the depth value retained by a low order Z-buffer memory with low order bits of the depth value calculated by the depth value calculation section. If a depth indicated by the high order bits of the depth value calculated by the depth value calculation section is shallow, the high order bits of the depth value retained by the high order Z-buffer memory and the low order bits of the depth value retained by the low order Z-buffer memory are updated.

Abstract: An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.

Abstract: In the case where a previous character (P1) is cleared on a screen (20) and a new character (P2) is displayed on the right of the previous one, first, image data to be transferred (P2) is prepared in a source image memory. Next, a write start address (W) is set at the head of a bit sequence of a left clearance width (LC)×BPP, which precedes the destination address (T) of a frame buffer into which the head (S) of the image data (P2) is to be written. After that, a series of burst transfer repeatedly copies clearance data held in a register into a region of the left clearance width (LC), starting from the write start address (W), and subsequently writes one line (a transfer width (W1)×BPP) of the image data (P2). The write start address is incremented by a frame width (FW)×BPP.

Abstract: An on-vehicle device, which is connected to an external image taking device via the Internet so as to allow communication therebetween, includes a communication section, a reception notification section, a display section, a vehicle stopped state detection section, and a display control section. When the communication section receives an emergency (or call) detection notification from the image taking device, the display control section checks the vehicle stopped state detection section to determine whether or not a vehicle is stopped. If the vehicle is stopped, the display control section receives video data from the image taking device via the communication section for causing the display section to display a video image of the video data. Otherwise, the display control section notifies a user of an emergency (or call) detection notification via the reception notification section.