Patents by Inventor Yorio Takada
Yorio Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230177248Abstract: Apparatuses, computer implemented methods and non-transitory computer-readable media storing instructions to implement simulating topological features of layout designs are disclosed. An example method includes: receiving information about the layout design including topological parameters in a verification area; defining a width and a length in first and second direction directions of one or more windows; defining first and second step sizes independently from the width and the length in the first and second directions for the one or more windows, the first step size being a distance between adjacent central points of the one or more windows in the first direction and the second step size being a distance between adjacent central points of the one or more windows in the second direction; extracting information about the layout design in the one or more windows at each of a plurality of window locations; and storing the information in a database.Type: ApplicationFiled: December 2, 2021Publication date: June 8, 2023Applicant: MICRON TECHNOLOGY, INC.Inventor: Yorio Takada
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Patent number: 11011471Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.Type: GrantFiled: December 9, 2019Date of Patent: May 18, 2021Assignee: Longitude Licensing LimitedInventors: Michio Inoue, Yorio Takada
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Publication number: 20200111746Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Inventors: Michio Inoue, Yorio Takada
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Patent number: 10504846Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.Type: GrantFiled: February 7, 2018Date of Patent: December 10, 2019Assignee: Longitude Licensing LimitedInventors: Michio Inoue, Yorio Takada
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Publication number: 20180166389Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.Type: ApplicationFiled: February 7, 2018Publication date: June 14, 2018Inventors: Michio Inoue, Yorio Takada
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Patent number: 9911699Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.Type: GrantFiled: November 15, 2016Date of Patent: March 6, 2018Assignee: Longitude Semiconductor S.a.r.l.Inventors: Michio Inoue, Yorio Takada
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Publication number: 20170062342Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.Type: ApplicationFiled: November 15, 2016Publication date: March 2, 2017Inventors: Michio INOUE, Yorio TAKADA
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Patent number: 9570378Abstract: A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern.Type: GrantFiled: May 20, 2014Date of Patent: February 14, 2017Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.Inventor: Yorio Takada
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Patent number: 9508650Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.Type: GrantFiled: October 24, 2014Date of Patent: November 29, 2016Assignee: Longitude Semiconductor S.a.r.l.Inventors: Michio Inoue, Yorio Takada
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Patent number: 9502354Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.Type: GrantFiled: November 28, 2014Date of Patent: November 22, 2016Assignee: Longitude Semiconductor S.a.r.l.Inventors: Michio Inoue, Yorio Takada
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Patent number: 9136203Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.Type: GrantFiled: May 7, 2014Date of Patent: September 15, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Yorio Takada, Kazuteru Ishizuka
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Publication number: 20150084184Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.Type: ApplicationFiled: November 28, 2014Publication date: March 26, 2015Inventors: Michio INOUE, Yorio TAKADA
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Publication number: 20150041970Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.Type: ApplicationFiled: October 24, 2014Publication date: February 12, 2015Inventors: Michio INOUE, Yorio TAKADA
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Patent number: 8895408Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.Type: GrantFiled: October 19, 2012Date of Patent: November 25, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Michio Inoue, Yorio Takada
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Publication number: 20140246780Abstract: A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern.Type: ApplicationFiled: May 20, 2014Publication date: September 4, 2014Applicant: Elpida Memory, Inc.Inventor: Yorio TAKADA
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Publication number: 20140239506Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Inventors: Yorio Takada, Kazuteru Ishizuka
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Patent number: 8756560Abstract: A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element pattern is not formed is planarized by a chemical mechanical polishing process, the method includes: setting an overall dummy section on the entire chip region; setting a mesh section on the entire overall dummy section; dividing the overall dummy section by the mesh section so that a plurality of rectangular dummy patterns is formed on the entire chip region after the mesh section is set; and removing or transforming a part of the rectangular dummy patterns, thereby uniformizing a density of the dummy pattern in the chip region.Type: GrantFiled: June 18, 2008Date of Patent: June 17, 2014Inventor: Yorio Takada
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Patent number: 8736063Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.Type: GrantFiled: June 3, 2013Date of Patent: May 27, 2014Inventors: Yorio Takada, Kazuteru Ishizuka
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Publication number: 20130264715Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.Type: ApplicationFiled: June 3, 2013Publication date: October 10, 2013Inventors: Yorio TAKADA, Kazuteru ISHIZUKA
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Patent number: 8502384Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.Type: GrantFiled: October 30, 2009Date of Patent: August 6, 2013Assignee: Elpida Memory, Inc.Inventors: Yorio Takada, Kazuteru Ishizuka