Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: Disclosed herein is the semiconductor substrate, wiring patterns and dummy patterns. A margin region is formed around the wiring pattern. The dummy region is further formed around the margin region. The dummy patterns are formed in the dummy region. The dummy patterns are arranged along the extending direction of the dummy region. Margin regions and dummy regions are allocated alternately with respect to the wiring pattern.

Abstract: An overlap amount definition section defines an amount of overlap between divided regions when a shape prediction objective region in a polished surface formed by chemical mechanical polishing is divided into a plurality of regions. A shape prediction computation processing section divides the objective region into the plurality of regions each of which includes a region corresponding to the overlap amount defined by the overlap amount definition section, and performs computation for shape prediction on each divided region by distributed processing. A merging processing section combines the results of shape prediction on the divided regions that are calculated by the shape prediction computation processing section.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.

Abstract: An overlap amount definition section defines an amount of overlap between divided regions when a shape prediction objective region in a polished surface formed by chemical mechanical polishing is divided into a plurality of regions. A shape prediction computation processing section divides the objective region into the plurality of regions each of which includes a region corresponding to the overlap amount defined by the overlap amount definition section, and performs computation for shape prediction on each divided region by distributed processing. A merging processing section combines the results of shape prediction on the divided regions that are calculated by the shape prediction computation processing section.

Abstract: A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element pattern is not formed is planarized by a chemical mechanical polishing process, the method includes: setting an overall dummy section on the entire chip region; setting a mesh section on the entire overall dummy section; dividing the overall dummy section by the mesh section so that a plurality of rectangular dummy patterns is formed on the entire chip region after the mesh section is set; and removing or transforming a part of the rectangular dummy patterns, thereby uniformizing a density of the dummy pattern in the chip region.

Abstract: A hotspot detection method for detecting a hotspot in a layout for a semiconductor device, includes: dividing a target analysis area into a grid based on layout data about the semiconductor device; and determining whether the grid falls into a hotspot or not, based on the results from simulation, using at least a detection criterion concerning a direction perpendicular to a direction of film thickness.

Abstract: A polishing apparatus includes a slurry supply arm arranged on a polish pad for a polishing target and extending from a center of the polish pad into a radius direction; a plurality of nozzles attached to the slurry supply arm to supply the slurry from the plurality of nozzles; and a plurality of pumps, each of which supplies the slurry to one of the plurality of nozzles. A control unit controls each of the plurality of pumps independently.