Patents by Inventor Yoshiaki Goto

Yoshiaki Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220327870
    Abstract: Provided is a driving evaluation device that enables evaluation of driving for the purpose of improving a driving time in a circuit racecourse. The driving evaluation device includes an evaluation section extractor 24 that detects a deceleration section and an acceleration section in cornering, a tire friction circle-load factor calculator 27 that calculates, based on a front-rear acceleration and a lateral acceleration, a tire friction circle and a tire load factor in the deceleration section and those in the acceleration section, and a skill deficiency evaluator 28 that evaluates driving based on the tire friction circle and the tire load factor in the deceleration section and those in the acceleration section.
    Type: Application
    Filed: February 25, 2022
    Publication date: October 13, 2022
    Inventors: Yuya GOTO, Yoshiaki KOBAYASHI, Toshiaki MATSUZAWA
  • Publication number: 20220319250
    Abstract: A driving assistance apparatus according to the present disclosure includes: a vehicle acceleration detection unit configured to detect vehicle acceleration including lateral acceleration and longitudinal acceleration of a vehicle; a calculation unit configured to calculate for each wheel a friction circle, and a lateral force generated at each wheel and a longitudinal force generated at each wheel on the basis of a result of detection by the vehicle acceleration detection unit; and a display unit configured to display an image based on the friction circle, and a magnitude and/or a direction of a resultant force of the lateral force and the longitudinal force generated at each wheel based on a result of calculation by the calculation unit.
    Type: Application
    Filed: February 24, 2022
    Publication date: October 6, 2022
    Inventors: Kenta Kakutani, Yoshiaki Kobayashi, Toshiaki Matsuzawa, Hideki Kakinuma, Yuya Goto, Ittoku Hirashima, Kimiyoshi Kusaka
  • Publication number: 20220319246
    Abstract: Provided is a driving evaluation device that enables evaluation of driving for the purpose of improving a driving time in a circuit racecourse, for example. The driving evaluation device includes an evaluation section extractor 24 that detects a deceleration section and an acceleration section in cornering, a section average classifier 25 that calculates, based on a front-rear acceleration and a lateral acceleration, an acceleration norm average value in the deceleration section and that in the acceleration section, and a skill deficiency evaluator 28 that evaluates driving skill based on the acceleration norm average value in the deceleration section and that in the acceleration section.
    Type: Application
    Filed: February 25, 2022
    Publication date: October 6, 2022
    Inventors: Yuya GOTO, Yoshiaki KOBAYASHI, Toshiaki MATSUZAWA
  • Patent number: 11402283
    Abstract: An electronic apparatus includes: an exterior body; a pressure-sensitive sensor having a sensing face; and a support supporting the pressure-sensitive sensor such that inner faces the exterior body is opposed to the sensing face.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 2, 2022
    Assignee: SONY CORPORATION
    Inventors: Tomoko Katsuhara, Akira Ebisui, Taizo Nishimura, Ken Kobayashi, Tetsuro Goto, Yoshiaki Sakakura, Kei Tsukamoto, Hayato Hasegawa, Manami Miyawaki
  • Patent number: 11378760
    Abstract: A connector assembly arrangement comprising, disposed on the faces of a circuit board in an electronic device, connector assemblies which, along with having a plug connector that incorporates a photoelectric conversion element capable of converting optical signals and electrical signals from one to the other and a receptacle connector with which said plug connector is mated, have the plug connector and the receptacle connector electrically connected through mutual contact between terminals; wherein the plug connector, from which a fiber optic cable for optical signal transmission that is connected to the photoelectric conversion element extends in one direction from said plug connector, also has terminals connected to the above-mentioned photoelectric conversion element; the fiber optic cable is a single fiber optic cable; and a plurality of connector assemblies are disposed on at least one of the two faces of the circuit board.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: July 5, 2022
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Naruki Ishida, Masayuki Goto, Yoshiaki Sano
  • Publication number: 20200388547
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Yoshiaki Goto
  • Patent number: 10840220
    Abstract: A semiconductor device of an embodiment includes a substrate, first, second, third, and fourth semiconductor elements, a first wiring layer, and first and second bonding wires. The third semiconductor element is on the substrate between the first resin element and the second resin element. The first wiring layer is on the first semiconductor element, is connected to the first semiconductor element, and is connected to the substrate by the first bonding wire. The fourth semiconductor element is on the first wiring layer and is connected to the first wiring layer by a second bonding wire. The first bonding wire is at a side of the first wiring layer other than a side farthest from the second wiring layer.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiaki Goto
  • Publication number: 20200303345
    Abstract: A semiconductor device of an embodiment includes a substrate, first, second, third, and fourth semiconductor elements, a first wiring layer, and first and second bonding wires. The third semiconductor element is on the substrate between the first resin element and the second resin element. The first wiring layer is on the first semiconductor element, is connected to the first semiconductor element, and is connected to the substrate by the first bonding wire. The fourth semiconductor element is on the first wiring layer and is connected to the first wiring layer by a second bonding wire. The first bonding wire is at a side of the first wiring layer other than a side farthest from the second wiring layer.
    Type: Application
    Filed: August 26, 2019
    Publication date: September 24, 2020
    Inventor: Yoshiaki GOTO
  • Patent number: 10777479
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshiaki Goto
  • Patent number: 10707193
    Abstract: According to one embodiment, a semiconductor device of an embodiment includes a substrate, a metal plate having a main portion having a first width in a first direction and a second width in a second direction orthogonal to the first direction, a first semiconductor chip located between the metal plate and the substrate, the first semiconductor chip having a third width in the first direction and a fourth width in the second direction, and a second semiconductor chip located between the first semiconductor chip and the substrate, wherein the first width is smaller than the third width, and the second width is smaller than the fourth width.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Yoshiaki Goto
  • Publication number: 20190244912
    Abstract: According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Yuusuke TAKANO, Yoshiaki GOTO, Takeshi WATANABE, Takashi IMOTO
  • Publication number: 20190139849
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 9, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Yoshiaki GOTO
  • Patent number: 10277006
    Abstract: Provided is a technology for suppressing variations in the waveform of a light emission pulse caused by various factors in a light-emitting device. A light-emitting device is provided with: a light source 101 in which relaxation oscillation occurs immediately after energization; a light source drive circuit 104 which includes a differentiation circuit 102 having a resistor and a capacitor connected in parallel, and in which a switching element 103 for voltage application is connected in series with the differentiation circuit; a power supply circuit 105; a light-reception element 107 which detects pulsed light emitted from the light source 101; and a voltage control unit 109 which controls an output voltage from the power supply circuit 105 in correspondence with the waveform of the detected pulsed light.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 30, 2019
    Assignee: TOPCON CORPORATION
    Inventors: Suguru Miyagawa, Yoshiaki Goto, Yoshikatsu Tokuda
  • Publication number: 20190088632
    Abstract: According to one embodiment, a semiconductor device of an embodiment includes a substrate, a metal plate having a main portion having a first width in a first direction and a second width in a second direction orthogonal to the first direction, a first semiconductor chip located between the metal plate and the substrate, the first semiconductor chip having a third width in the first direction and a fourth width in the second direction, and a second semiconductor chip located between the first semiconductor chip and the substrate, wherein the first width is smaller than the third width, and the second width is smaller than the fourth width.
    Type: Application
    Filed: March 1, 2018
    Publication date: March 21, 2019
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI, Yoshiaki GOTO
  • Patent number: 10207668
    Abstract: A side airbag device includes a folded-up airbag and a limitation member disposed around the airbag for constraining the airbag from protruding forward at airbag deployment. The limitation member is formed of a flexible sheet member into a band shape, and is joined to the folded-up airbag by the opposite end regions. The limitation member includes a loose region which is arranged around the folded-up airbag in such a manner as to be remote from the folded-up airbag. The loose region is disposed on a side of the folded-up airbag towards which the airbag protrudes. The loose region includes a tearable region in the region in a deployment direction of the airbag.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: February 19, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yoshiaki Goto, Kensaku Honda, Akira Suzuki, Masao Kino
  • Patent number: 10199300
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiaki Goto
  • Patent number: 9985415
    Abstract: Light with a short pulse width is emitted using a simple structure. A light source 101, a differentiation circuit 102, and a switch 103 are connected in series. When the switch 103 is switched on, inrush current flows in a capacitor 102b forming the differentiation circuit 102, and accordingly the light source 101 is supplied with electric current and thereby emits light. When the capacitor 102b is charged, electric current flows in a resistor 102a, and voltage drops at the resistor 102a. Then, the voltage applied to the light source 101 is decreased, whereby the light source 101 stops emitting light. By using the inrush current at the capacitor 102b, light with a short pulse width can be generated.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 29, 2018
    Assignee: KABUSHIKI KAISHA TOPCON
    Inventors: Yoshikatsu Tokuda, Yoshiaki Goto
  • Publication number: 20180109073
    Abstract: Provided is a technology for suppressing variations in the waveform of a light emission pulse caused by various factors in a light-emitting device. A light-emitting device is provided with: a light source 101 in which relaxation oscillation occurs immediately after energization; a light source drive circuit 104 which includes a differentiation circuit 102 having a resistor and a capacitor connected in parallel, and in which a switching element 103 for voltage application is connected in series with the differentiation circuit; a power supply circuit 105; a light-reception element 107 which detects pulsed light emitted from the light source 101; and a voltage control unit 109 which controls an output voltage from the power supply circuit 105 in correspondence with the waveform of the detected pulsed light.
    Type: Application
    Filed: April 28, 2016
    Publication date: April 19, 2018
    Applicant: TOPCON CORPORATION
    Inventors: Suguru MIYAGAWA, Yoshiaki GOTO, Yoshikatsu TOKUDA
  • Patent number: 9873399
    Abstract: An airbag in an uninflated-and-spread form includes a rear-lower inflation portion and a front-upper inflation portion. The airbag is stored in a first vehicle seat. The vehicle seat adjacent to the first vehicle seat is a second vehicle seat. The front-upper inflation portion includes at least three bend portions, which are arranged in a flowing direction of inflation gas. A form between the uninflated-and-spread form and the storage form is a transitional form. In the transitional form, the bend portions are each bent relative to the adjacent bend portion and rolled toward the second vehicle seat relative to the rear-lower inflation portion such that the closer a bend portion is to the downstream end, the more inward the bend portion is located. In the transitional form, the upper end of the most upstream bend portion is connected to the upper end of the rear-lower inflation portion.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: January 23, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yoshiaki Goto, Yuji Matsuzaki, Yasushi Masuda
  • Patent number: 9701270
    Abstract: A side airbag system includes: an airbag; and a wrapping material that is disposed around a folded-up airbag body into which the airbag is folded so as to prevent the collapse of neatly arranged folds of the folded-up airbag body, the folded-up airbag body being configured as an elongated body having an external shape that is disposed so that a longitudinal direction thereof substantially follows an up-to-down direction, wherein: the wrapping material is disposed so as to wrap around the folded-up airbag body, including a brake planned portion capable of breaking when the airbag inflates which is provided on a front surface side of the folded-up airbag body so as to substantially follow the up-to-down direction; and the break planned portion comprises a low-strength portion where a break strength thereof is set low and a high-strength portion where the break strength is set high.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 11, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yoshiaki Goto, Kensaku Honda, Akira Suzuki, Masao Kino