Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.

Abstract: A semiconductor memory device includes a substrate, a plurality of bit lines extending in a first direction parallel to a main surface of the substrate, a plurality of selection gates extending in a second direction perpendicular to the first direction, and a contact region between the selection gates on the substrate and includes a plurality of contacts respectively formed under the bit lines. The contact region is formed so that N (N?3) contacts are disposed under the N adjacent bit lines on a straight line that is not parallel to the first and second directions. A first dummy contact is located under a first bit line of the N adjacent bit lines, and a second dummy contact located under the N-th bit line among the N adjacent bit lines.

Abstract: A semiconductor storage device including a memory cell array including a memory cell and a circuit element including first wirings and a selection element, the first wirings having a wiring width smaller than a resolution limit of an exposure apparatus. The first wirings extend in a first direction and are aligned in a second direction crossing with the first direction. A second wiring, being one of the first wirings, is cut by at least one cut region. The first wiring adjacent to the second wiring in the second direction extends continuously in the first direction in a portion adjacent to the cut region in the second direction.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first region and a second region, a first insulating layer provided above the semiconductor layer, an extending first contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a first element provided in the first region, an extending second contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a second element provided in the second region, an extending first interconnection layer connected to an upper end of the first contact electrode, and having a sidewall surrounded with the first insulating layer, and an extending second interconnection layer connected to an upper end of the second contact electrode, having a sidewall surrounded with the first insulating layer, and having a line width wider than a line width of the first interconnection layer.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of mask patterns by anisotropically etching a mask-forming film until upper surfaces of core patterns are exposed. A facing pair includes a pair of the mask patterns facing the core pattern located between the paired mask patterns. The mask patterns of the facing pair have respective lower portions spaced from each other by a first distance. An adjacent pair includes a pair of mask patterns adjacent to each other with a space having no core pattern. The mask patterns of the adjacent pair have respective lower portions spaced from each other by a second distance. The mask patterns are formed so that the second distance is larger than the first distance.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a plurality of first buried wirings and a plurality of second buried wirings located in the insulating film at predetermined intervals alternately in a direction parallel to a surface of the semiconductor substrate. Each second buried wiring is formed so that a width between both side surfaces thereof is increased from a lower end toward an upper portion and at an upper surface the width is larger than a width at an upper surface of each first buried wiring.

Abstract: In accordance with an embodiment, a semiconductor device includes a substrate, a first insulating film on the substrate, wiring lines including a metal in trenches in the first insulating film, and a second insulating film. The second insulating film covers the first insulating film and the wiring line. The trenches are arranged parallel to one another at predetermined intervals. The dielectric constant of the material of the second insulating film is higher than that of the first insulating film. The lower surface of the second insulating film in a region between the wiring lines locates above a surface that connects the peripheral edges of the upper surfaces of the wiring lines.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of mask patterns by anisotropically etching a mask-forming film until upper surfaces of core patterns are exposed. A facing pair includes a pair of the mask patterns facing the core pattern located between the paired mask patterns. The mask patterns of the facing pair have respective lower portions spaced from each other by a first distance. An adjacent pair includes a pair of mask patterns adjacent to each other with a space having no core pattern. The mask patterns of the adjacent pair have respective lower portions spaced from each other by a second distance. The mask patterns are formed so that the second distance is larger than the first distance.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A first aspect of the present invention is providing a non-volatile semiconductor memory device, comprising: a memory cell having a tunnel oxide layer formed on a semiconductor substrate, a floating gate formed on the tunnel oxide layer, a control gate to which voltage is supplied, a source diffusion layer and a drain diffusion layer, the source and drain diffusion layers formed in the semiconductor substrate adjacent to the tunnel oxide layer; a contact layer connected to the drain diffusion layer; and a layer formed above the memory cell, the layer comprising at least one of: 1) a silicon oxide layer to which nitrogen are doped, 2) a silicon oxide layer to which aluminum are doped, 3) an aluminum oxide layer, 4) a silicon oxide layer to which titanium are doped, 5) a silicon oxide layer to which two of nitrogen, aluminum, and titanium are doped, 6) a silicon oxide layer to which nitrogen, aluminum, and titanium are doped, 7) a titanium oxide layer, 8) a titanium and aluminum oxide layer, 9) a simple metal l

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed inself-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A nonvolatile memory device having a gate electrode including: a non volatile memory cell configured to store data, and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor having a second gate electrode, third and fourth diffusion layers, the second gate electrode having a second top surface and a second side surface, and a width between the third and fourth diffusion layers of the second gate electrode being wider than that between the first and second diffusion layers of the first gate electrode; a first contact layer connected to the second top surface of the second gate electrode of the peripheral transistor; and a silicon nitride layer formed above the first side surface of the first gate electrode in the non volatile memory cell and the second side surface of the second gate electrode in the peripheral transistor, the silicon nitride layer not being contact with the first contact layer, a

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.