Abstract: A nonvolatile memory device having a gate electrode including: a non volatile memory cell configured to store data, and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor having a second gate electrode, third and fourth diffusion layers, the second gate electrode having a second top surface and a second side surface, and a width between the third and fourth diffusion layers of the second gate electrode being wider than that between the first and second diffusion layers of the first gate electrode; a first contact layer connected to the second top surface of the second gate electrode of the peripheral transistor; and a silicon nitride layer formed above the first side surface of the first gate electrode in the non volatile memory cell and the second side surface of the second gate electrode in the peripheral transistor, the silicon nitride layer not being contact with the first contact layer, a

Abstract: A method for manufacturing a semiconductor memory device having a memory region and a peripheral region, including forming a memory cell on the memory region and a peripheral transistor on the peripheral region, the memory cell having a first gate electrode and a first diffusion layer, the peripheral transistor having a second gate electrode and a second diffusion layer; forming a silicon nitride layer above an upper surface and a side surface of the first gate electrode of the memory cell and above an upper surface and a side surface of the second gate electrode of the peripheral transistor; removing the silicon nitride layer that is formed above the upper surface of the second gate electrode of the peripheral transistor; forming an interlayer insulating film above the memory cell and the peripheral transistor; forming a first contact hole that reaches the upper surface of the second gate electrode of the peripheral transistor by removing a portion of the interlayer insulating film; and forming a conductive

Abstract: A method for manufacturing a semiconductor memory device having a memory region and a peripheral region, including forming a memory cell on the memory region and a peripheral transistor on the peripheral region, the memory cell having a first gate electrode and a first diffusion layer, the peripheral transistor having a second gate electrode and a second diffusion layer; forming a silicon nitride layer above an upper surface and a side surface of the first gate electrode of the memory cell and above an upper surface and a side surface of the second gate electrode of the peripheral transistor; removing the silicon nitride layer that is formed above the upper surface of the second gate electrode of the peripheral transistor; forming an interlayer insulating film above the memory cell and the peripheral transistor; forming a first contact hole that reaches the upper surface of the second gate electrode of the peripheral transistor by removing a portion of the interlayer insulating film; and forming a conductive

Abstract: A semiconductor memory device having a memory region and a peripheral region, comprising: a memory cell configured to store data, the memory cell formed in the memory region of a semiconductor substrate and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor formed in the peripheral region in the semiconductor substrate having a second gate electrode, third and fourth diffusion layers, the second gate electrode having a second top surface and a second side surface; a first contact layer connected to the second top surface of the second gate electrode in the peripheral transistor; and a silicon nitride layer formed above the first side surface of the first gate electrode in the memory cell and the second side surface of the second gate electrode in the peripheral transistor, the silicon nitride layer not being contact with the first contact layer, a thickness of the silicon nitride layer that is

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A semiconductor memory device having a memory region and a peripheral region, comprising: a memory cell configured to store data, the memory cell formed in the memory region of a semiconductor substrate and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor formed in the peripheral region in the semiconductor substrate having a second gate electrode, third and fourth diffusion layers, the second gate electrode having a second top surface and a second side surface; a first contact layer connected to the second top surface of the second gate electrode in the peripheral transistor; and a silicon nitride layer formed above the first side surface of the first gate electrode in the memory cell and the second side surface of the second gate electrode in the peripheral transistor, the silicon nitride layer not being contact with the first contact layer, a thickness of the silicon nitride layer that is

Abstract: A first aspect of the present invention is providing a semiconductor memory device having a gate electrode, comprising a memory cell having the gate, a source electrode, and a drain electrode; and a layer formed above the memory cell, the layer comprising at least one of: 1) a silicon oxide layer to which nitrogen are doped, 2) a silicon oxide layer to which aluminum are doped, 3) an aluminum oxide layer, 4) a silicon oxide layer to which titanium are doped, 5) a silicon oxide layer to which two of nitrogen, aluminum, and titanium are doped, 6) a silicon oxide layer to which nitrogen, aluminum, and titanium are doped, 7) a titanium oxide layer, 8) a titanium and aluminum oxide layer, 9) a simple metal layer comprising one of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, 10) an alloy layer comprising at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, and the at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc being included 50% or more, 11) a nitrogenous layer of the alloy layer

Abstract: A semiconductor device has a structure in which a gate electrode formed on a semiconductor substrate is buried in an interlevel insulating film so that the upper surface of the gate electrode is exposed, and an insulating film not containing boron and phosphorous is formed on this gate electrode. In this structure, the film thickness of the interlevel insulating film is small. This reduces the aspect ratio of a contact hole and improves the quality of burying of the contact hole. Since no interlevel insulating film which usually contains boron and phosphorous exists on the gate electrode, a shape change of the contact hole caused by annealing can be suppressed. This can improve the reliability of contact.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A projection lens for projecting an image appearing on a CRT onto a large-sized screen, comprising, from the screen side a first lens structure including a meniscus lens having both surfaces convex toward the screen, a second lens structure comprising a cemented glass lens, a single glass lens and a plastic aspherical lens, and third lens structure of negative power with one concave surface toward the screen. Locating the aspherical surface on the plastic lens, and providing most of the lens power with the glass lenses, achieves low cost of manufacture, light weight, little chromatic aberration, and little change of focal length with change of temperature.

Abstract: A projection lens for magnifying and projecting an image appearing on a CRT onto a large screen, comprising, from the screen side, a first lens means including a meniscus lens having both surface convex relative to the screen, a second lens means of positive power and a third lens means group of negative power. The projection lens satisfies the following conditions:0.0<f/f.sub.1 <0.11.0<r.sub.1 /f<9.7f being the focal length of the overall lens, f.sub.1 the focal length of the first lens means and r.sub.1 the radius of curvature of the screen side surface of the meniscus lens.

Abstract: Removal of hydrogen impurities from a secondary cooling system of a liquid sodium cooled, fast breeder reactor is accomplished by providing a hydrogen-removing container, which may be a tank, in the secondary cooling system. The container has a sodium coolant inlet and outlet means, a gas phase zone statically containing a cover gas therein, and a cover gas inlet and outlet means. Sodium mist is deposited on the inner surface of the gas phase zone which faces the cover gas and functions as a hydrogen-getter means. Thus, the sodium mist deposit captures and accumulates hydrogen previously accumulated in the cover gas. By intermittently heating the inner surface of the container, the hydrogen captured by the sodium mist deposit is released into the cover gas. The hydrogen-containing cover gas is then discharged from the system and fresh cover gas is contemporaneously introduced and may be obtained by refining the hydrogen-containing cover gas to render it fresh and reusable.

Abstract: An apparatus for detecting the leakage of liquid sodium includes a cable-like sensor adapted to be secured to a wall of piping or other equipment having sodium on the opposite side of the wall, and the sensor includes a core wire electrically connected to the wall through a leak current detector and a power source. An accidental leakage of the liquid sodium causes the corrosion of a metallic layer and an insulative layer of the sensor by products resulted from a reaction of sodium with water or oxygen in the atmospheric air so as to decrease the resistance between the core wire and the wall. Thus, the leakage is detected as an increase in the leaking electrical current. The apparatus is especially adapted for use in detecting the leakage of liquid sodium from sodium-conveying pipes or equipment in a fast breeder reactor.