Patents by Inventor Yoshiaki Kamigaki
Yoshiaki Kamigaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040065918Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.Type: ApplicationFiled: October 2, 2003Publication date: April 8, 2004Applicant: Hitachi, Ltd.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Patent number: 6674122Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: GrantFiled: March 4, 2003Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Patent number: 6653685Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.Type: GrantFiled: November 20, 2001Date of Patent: November 25, 2003Assignee: Hitachi, Ltd.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Publication number: 20030155607Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is formed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: ApplicationFiled: March 4, 2003Publication date: August 21, 2003Applicant: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Patent number: 6590809Abstract: When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.Type: GrantFiled: January 9, 2002Date of Patent: July 8, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takanori Yamazoe, Hiroshi Yoshigi, Yoshiaki Kamigaki, Kozo Katayama, Shinichi Minami, Takeo Kanai
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Patent number: 6531735Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: GrantFiled: September 13, 2000Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Publication number: 20030017672Abstract: Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction.Type: ApplicationFiled: September 18, 2002Publication date: January 23, 2003Applicant: Hitachi, Ltd.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Publication number: 20020179963Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.Type: ApplicationFiled: June 10, 2002Publication date: December 5, 2002Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Publication number: 20020131299Abstract: When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.Type: ApplicationFiled: January 9, 2002Publication date: September 19, 2002Applicant: Hitachi, Ltd.Inventors: Takanori Yamazoe, Hiroshi Yoshigi, Yoshiaki Kamigaki, Kozo Katayama, Shinichi Minami, Takeo Kanai
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Patent number: 6451643Abstract: A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.Type: GrantFiled: June 5, 2001Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Publication number: 20020074594Abstract: Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction.Type: ApplicationFiled: November 20, 2001Publication date: June 20, 2002Applicant: Hitachi, Ltd.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Publication number: 20010038119Abstract: A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.Type: ApplicationFiled: June 5, 2001Publication date: November 8, 2001Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Publication number: 20010013611Abstract: A plurality of connection holes 24 for connecting n+ type semiconductor region 20 of zener diodes (D1, D2) and wires 21 and 22 to each other are not arranged in the center of the n+ type semiconductor region 20, that is, in a region in which a p+ type semiconductor region 6 and the n+ type semiconductor region 20 form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes 24 are spaced from each other so that a pitch between the adjacent connection holes 24 is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes 24 are formed by means of dry etching.Type: ApplicationFiled: January 25, 2001Publication date: August 16, 2001Inventors: Shinichi Minami, Yoshiaki Kamigaki, Hideki Yasuoka, Fukuo Owada
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Patent number: 6255690Abstract: A semiconductor memory device having nonvolatile memory cells of a single-element type. The nonvolatile memory cells have a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. An impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode.Type: GrantFiled: March 31, 1999Date of Patent: July 3, 2001Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5904518Abstract: A method of manufacturing a semiconductor memory device having nonvolatile memory cells of a single-element type. The method provides for the formation of a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. Also by this method, an impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode.Type: GrantFiled: June 30, 1997Date of Patent: May 18, 1999Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5656839Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.Type: GrantFiled: April 17, 1995Date of Patent: August 12, 1997Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5656522Abstract: A method of manufacturing a semiconductor memory device having non-volatile memory elements or memory cells of a single-element type. The method provides for the formation of a floating gate electrode on a main surface of a semiconductor substrate and a control gate electrode on the floating gate electrode via a second gate insulating film. In accordance with the method, an impurity is introduced in self-alignment with one of a pair of opposing end portions of the control gate electrode to form a first semiconductor region, and on the second of the opposing end portions of the control gate electrode of the memory cell, the same impurity, for example, arsenic, but, however, of a lower dose is introduced in self-alignment to form a second semiconductor region.Type: GrantFiled: May 30, 1995Date of Patent: August 12, 1997Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5629541Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.Type: GrantFiled: April 17, 1995Date of Patent: May 13, 1997Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5407853Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.Type: GrantFiled: January 11, 1994Date of Patent: April 18, 1995Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5300802Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.Type: GrantFiled: May 20, 1991Date of Patent: April 5, 1994Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki