Patents by Inventor Yoshiaki Kato

Yoshiaki Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8000758
    Abstract: A portable terminal device having a folding structure includes a body unit 20 having operation keys 21, a display unit 10 movably connected to the body unit 20 and having a display 11 on an opposite surface to the operation keys 21 when folded, and a protruded portion 12, for preventing damage to the display, provided along an outer edge portion of the display 11 on the opposite surface of the display unit 10 and formed so that its height on the connecting side to the body unit 20 is smaller than on the side of a free end of the display unit 10.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Limited
    Inventors: Toshiyuki Itoh, Shigeru Yamaguchi, Hiroshi Kobayashi, Yoshiaki Kato
  • Publication number: 20110176221
    Abstract: In one example embodiment, a liquid lens includes a pair of transparent members and a transparent liquid composed of a silicone oil not having compatibility with the fluorinated elastomeric membrane. In one example embodiment, at least one of the transparent members is a deformable deformation membrane formed of a fluorinated elastomeric membrane. In one example embodiment, the transparent liquid fills an enclosed space sandwiched between the pair of transparent members.
    Type: Application
    Filed: September 16, 2009
    Publication date: July 21, 2011
    Applicant: Sony Corporation
    Inventors: Kayoko Tanaka, Yoshiaki Kato, Fumisada Maeda, Akira Suzuki, Sachiko Sakaigawa
  • Patent number: 7982790
    Abstract: To provide a solid-state imaging apparatus which is capable of preventing electric charge from being injected from a semiconductor substrate while electric charge is being accumulated into photodiodes. The solid-state imaging apparatus includes a solid-state imaging device and a driving pulse control unit. The solid-state imaging device includes: a semiconductor substrate, photodiodes which are two-dimensionally formed on the semiconductor substrate, and vertical Charge-coupled devices (CCDs) having at least one arranged read-out gate and non-read-out gate for each of the photodiodes, the read-out gate being for reading out accumulated electric charge from the associated photodiode, and the non-read-out gate being not for reading out accumulated electric charge from the associated photodiode.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventor: Yoshiaki Kato
  • Patent number: 7978400
    Abstract: An electro-wetting apparatus includes a liquid having conductivity or polarity and a first electrode and a second electrode that apply voltage to the liquid. The electro-wetting apparatus also includes a dielectric layer provided between the liquid and the first electrode. The electro-wetting apparatus further includes a voltage-applying unit that applies a voltage signal between the first electrode and the second electrode, where the voltage signal is periodically changed between a first voltage of zero (0) volt or more and a second voltage of larger than the first voltage.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: July 12, 2011
    Assignee: Sony Corporation
    Inventors: Yoshihiro Takemoto, Yoshiaki Kato, Fumisada Maeda
  • Publication number: 20110164162
    Abstract: A solid-state imaging device includes vertical transfer units each of which is configured to transfer charge read from light receiving units, a first horizontal transfer unit and a second horizontal transfer unit each of which includes a plurality of transfer gate electrodes arranged in parallel to one another, a sorting transfer unit configured to transfer charge between the horizontal transfer units, and an output unit. In the first horizontal transfer unit, the transfer gate electrodes extend from the vertical transfer units toward the sorting transfer unit, and at least a part of each of the plurality of transfer gate electrodes located closer to the vertical transfer units is obliquely extends so that a horizontal distance from the output unit increases as it extends toward the sorting transfer unit.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Yoshiaki KATO
  • Publication number: 20110129016
    Abstract: Provided are a device and a method for efficiently compressing information by performing improved removal of signal correlations according to statistical and local properties of a video signal in a 4:4:4 format which is to be encoded. The device includes: a prediction unit for determining, for each color component, a motion prediction mode exhibiting a highest efficiency among a plurality of motion prediction modes, and detecting a motion vector corresponding to the determined motion prediction mode, to thereby perform output; and a variable-length encoding unit for determining, when performing arithmetic coding on the motion prediction mode of the each color component, an occurrence probability of a value of the motion prediction mode of the each color component based on a motion prediction mode selected in a spatially-adjacent unit region and a motion prediction mode selected in a temporally-adjacent unit region, to thereby perform the arithmetic coding.
    Type: Application
    Filed: July 3, 2009
    Publication date: June 2, 2011
    Inventors: Shunichi Sekiguchi, Shuichi Yamagishi, Yusuke Itani, Yoshihisa Yamada, Yoshiaki Kato, Kohtaro Asai, Tokumichi Murakami
  • Publication number: 20110129995
    Abstract: A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
    Type: Application
    Filed: February 8, 2011
    Publication date: June 2, 2011
    Applicant: Panasonic Corporation
    Inventors: Shinichi Domae, Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano
  • Publication number: 20110075002
    Abstract: A solid-state imaging device includes vertical transfer units each including first and second transfer units. A drive control unit controls transfer processes of the vertical transfer units so that (i) after transferring a packet, the first transfer unit stops transferring another packet in a period during which the packet is horizontally transferred, (ii) the second transfer unit in the same group transfers the packet to a horizontal transfer unit at a timing different from a timing at which another second transfer unit in the same group transfers a different packet to the horizontal transfer unit, (iii) the horizontal transfer unit horizontally transfers the received packet in a horizontal transfer period different from another horizontal transfer period during which the different packet is horizontally transferred, and (iv) at least one charge transfer stage serving as the well region differs between these horizontal transfer periods.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 31, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Yoshiaki KATO
  • Patent number: 7911060
    Abstract: A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Shinichi Domae, Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano
  • Patent number: 7904781
    Abstract: A data transmitting device and a data receiving device which are capable of conducting an error correction using an FEC stream without requiring a feedback from the data receiving device to the data transmitting device are obtained. The data receiving device includes a media packet transmitting unit for transmitting media streams, a plurality of FEC packet calculating units for calculating FEC packets having different parameters, and a plurality of FEC packet transmitting units for transmitting the FEC packets as a FEC stream. Further, the data receiving device includes a media packet receiving unit for acquiring the media packets, an FEC stream selecting and receiving unit for selecting one or a plurality of FEC streams from the plurality of FEC streams to acquire the FEC packets, and a media packet restoring unit for restoring a lost packet by using the FEC packet.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 8, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toyokazu Sugai, Yoshiaki Kato
  • Patent number: 7884872
    Abstract: A driving method is applied to a solid-state imaging apparatus having photoelectric conversion portions, transfer portion for reading out signal charges, and an excess charge draining portion for draining charges exceeding a saturation charge amount that is set by a reference voltage. One of driving modes is selected from a full pixel mode in which accumulated signal charges are detected individually for each pixel and a pixel mixing mode in which signal charges of a predetermined number of pixels are mixed to be detected. In the full pixel mode, the draining portion is supplied with the reference voltage having the same value during a charge accumulation period and a read transfer period for read transferring charges. In the pixel mixing mode, the draining portion is supplied with the reference voltage having a low level during the charge accumulation period and the reference voltage having a high level during the read transfer period.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: February 8, 2011
    Assignee: Panasonic Corporation
    Inventors: Tsuyoshi Hasuka, Ryoichi Nagayoshi, Keijirou Itakura, Izumi Shimizu, Yoshiaki Kato
  • Publication number: 20110024605
    Abstract: An imaging apparatus capable of suppressing deterioration of image qualities and output properties is provided having one or more output circuits in series and a buffer circuit 6, and processing luminance signals from photodetectors to output image information, the buffer circuit performing impedance conversion on signals outputted from a final output circuit of the one or more output circuits, the final output circuit being a source follower circuit that has an active element and a current source circuit 5 which is inserted between a source terminal of the active element and a reference voltage terminal, wherein the current source circuit and the buffer circuit 6 are external to a solid-state image sensor 1 having the photodetectors, and a main part of the current source circuit 5 and a main part of the buffer circuit 6 are in a single package.
    Type: Application
    Filed: August 17, 2010
    Publication date: February 3, 2011
    Applicant: Panasonic Corporation
    Inventors: Akiyoshi Kohno, Yoshiaki Kato, Yuji Matsuda
  • Publication number: 20110025824
    Abstract: First macro photography is performed with each of the imaging systems being focused on a main subject to obtain first images, second photography is performed with one of the plurality of imaging systems being focused on a position farther away than the main subject to obtain a second image, processing is performed on each of the first images to transparentize an area other than the main subject, and each of the transparentized first images and an area other than the main subject of the second image are combined to generate a combined image corresponding to each of the imaging systems.
    Type: Application
    Filed: July 22, 2010
    Publication date: February 3, 2011
    Applicant: FUJIFILM CORPORATION
    Inventors: Yoshiaki KATO, Toshinori Miyamura, Akihiko Shimeno
  • Patent number: 7863633
    Abstract: The solid-state imaging device of the present invention includes: photodiodes which are two-dimensionally arranged; light condensers each of which condenses light and is provided in a position to correspond to two of the photodiodes which are adjacent to each other; and separating units each of which separates the light entering through the light condensers into first light having a wavelength within a predetermined range, and second light having a wavelength out of the predetermined range, and is provided in a position to correspond to one of the light condensers.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: January 4, 2011
    Assignee: PANASONIC Corporation
    Inventor: Yoshiaki Kato
  • Patent number: 7847849
    Abstract: A solid-state imaging device includes: a plurality of light-receiving elements which are arranged by rows and columns. A driving unit performs a driving, so that a signal packet and a plurality of dummy packets in an identical column are mixed together into a mixed packet in each holding units, charges of the mixed packet are held in a hold unit, the held charges of the mixed packet are vertically transferred to a horizontal transfer unit so that the mixed packet is mixed with a mixed packet of a different hold unit which is vertically transferred from the different hold unit to the horizontal transfer unit.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventor: Yoshiaki Kato
  • Patent number: 7835403
    Abstract: An analysis display has a coordinate plane of which coordinate axes are elapsed time and PCR (Program Clock Reference) time calculated using PCR extracted from header information of a transport stream packet. A box indicator representing an access unit is provided on the coordinate plane and sides of the box indicator indicate an arrival time of the access unit AU and time of time stamps PTS/DTS. It analyzes the PCR in a transport stream layer and the time stamps PTS/DTS in a PES layer in a manner of over layers, and displays an analysis result that allows easily understanding a relationship between system timing and them. Therefore, it makes it easier to check a problem on the PCR and the time stamps PTS/DTS.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: November 16, 2010
    Assignee: Tektronix, Inc.
    Inventor: Yoshiaki Kato
  • Patent number: 7829957
    Abstract: A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshiaki Kato, Yoshiharu Anda, Akihiko Nishio
  • Patent number: 7818779
    Abstract: According to the present invention, in a content delivery managing section 16, transmission channels and transmission timing are allocated to contents layered according to content properties or respective contents constituting a program. In a content transmission section 10, on the basis of the transmission channels and transmission timing allocated in the content delivery managing section 16, coded bit sequences 101a to 101n of respective contents are multiplexed with timing information 102 such as decoding timing information, combination timing information, presentation timing information and reproduction start timing information for the contents generated in a timing information generating section 14 to generate transmission bit sequences 105a to 105n, and they are transmitted.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: October 19, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Matsuzaki, Yoshiaki Kato
  • Patent number: 7813571
    Abstract: An image encoding apparatus includes a converter 1 for receiving an image signal, and for converting the image signal of individual blocks to DC components and AC components by orthogonal transformation of the individual blocks of an image frame; a predicted reference value generator 2 for receiving the image signal, and for generating a predicted reference value of each image frame from DC components resulting from the orthogonal transformation of left-edge blocks of the image frame; and a differential unit 3 for obtaining difference values between the DC components output from the converter 1 and the predicted reference value generated by the predicted reference value generator 2. The image encoding apparatus outputs a bit stream by quantizing and variable-length encoding the AC components and difference values obtained by the differential unit 3, and by quantizing and variable-length encoding the predicted reference value to be added to a header.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: October 12, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daiki Kudo, Yoshihisa Yamada, Hirofumi Nishikawa, Yoshiaki Kato
  • Patent number: 7795571
    Abstract: An imaging apparatus capable of suppressing deterioration of image qualities and output properties is provided having one or more output circuits in series and a buffer circuit 6, and processing luminance signals from photodetectors to output image information, the buffer circuit performing impedance conversion on signals outputted from a final output circuit of the one or more output circuits, the final output circuit being a source follower circuit that has an active element and a current source circuit 5 which is inserted between a source terminal of the active element and a reference voltage terminal, wherein the current source circuit and the buffer circuit 6 are external to a solid-state image sensor 1 having the photodetectors, and a main part of the current source circuit 5 and a main part of the buffer circuit 6 are in a single package.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Akiyoshi Kohno, Yoshiaki Kato, Yuji Matsuda