Patents by Inventor Yoshiaki Matsushita

Yoshiaki Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5004702
    Abstract: A semiconductor substrate having a surface region of P type and a surface region of N type is formed, then an insulating membrane is formed on the semiconductor substrate. The first contact hole which is formed in said region of P type and the second contact hole which is connected to said region of N type are formed by the same process as that for said insulating membrane. Non-doped silicon layer is grown in said first and second contact holes by the same selective growth process, in a single reactive furnace. A diffusion source layer containing impurities of P type is formed on said first contact hole and a diffusion source layer containing impurities of N type on said second contact hole. Impurities are diffused from said diffusion layers to said silicon layers, and said diffusion source layer is then removed. A metal wire layer is formed by connecting it to said silicon layer.
    Type: Grant
    Filed: April 17, 1989
    Date of Patent: April 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Samata, Yoshiaki Matsushita
  • Patent number: 4894349
    Abstract: A process for forming a vapor-phase epitaxial growth layer on a silicon wafer having a buried layer of a high As or B concentration. This vapor-phase epitaxial growth process is performed in two steps of (i) performing a vapor-phase epitaxial growth at a relatively low temperature by using a reaction gas containing at least one kind selected from a group consisting of SiH.sub.x F.sub.4-x (x=0 to 3) and Si.sub.2 H.sub.x F.sub.6-x (x=0-5) and at least one kind selected from a group consisting of SiH.sub.4 and Si.sub.2 H.sub.6, and (ii) performing a vapor-phase epitaxial growth under a condition which allows a higher growth rate that in the step (i) by using a reaction gas containing SiH.sub.4 or Si.sub.2 H.sub.6 which may or may not be accompanied with silane fluoride.
    Type: Grant
    Filed: December 15, 1988
    Date of Patent: January 16, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiko Saito, Yoshiaki Matsushita
  • Patent number: 4894206
    Abstract: The present invention discloses a crystal pulling apparatus having a double-crucible structure, wherein an inner crucible is located in an outer crucible. An end of a pipe-like passage is located in a through hole formed in a side wall of an inner crucible located in an outer crucible, and a melt is supplied from the outer crucible to the inner crucible through the pipe-like passage, during crystal pulling. During melting or neckdown, prior to crystal pulling, diffusion of an impurity between the melts in the outer crucible and the inner crucible, and exchange of the melts between the outer crucible and the inner crucible are prevented by the pipe-like passage.
    Type: Grant
    Filed: September 1, 1987
    Date of Patent: January 16, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Youji Yamashita, Masakatu Kojima, Yoshiaki Matsushita, Masanobu Ogino
  • Patent number: 4885257
    Abstract: A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than 1100.degree. C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from 600.degree. to 900.degree. C. and providing a single crystal semiconductor layer.
    Type: Grant
    Filed: June 2, 1987
    Date of Patent: December 5, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Matsushita
  • Patent number: 4862000
    Abstract: In a method for predicting a density of micro crystal defects to be generated in a semiconductor element, an infrared absorption spectrum associated with a silicon wafer, which is used for the manufacture of the semiconductor element, is formed by a spectrum forming system. The spectrum has a first oxygen absorption peak at the wavenumber range of 1150 to 1050 cm.sup.-1 and a second oxygen absorption peak at 530 to 500 cm.sup.-1. First and second coefficients indicating oxygen concentrations at the first and second peaks are read by a reading unit. The density of the micro crystal defects are predicted by using a ratio of the first and second coefficients as a monitor.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: August 29, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kubota, Yoshiaki Matsushita, Yoshiaki Ohwada
  • Patent number: 4837610
    Abstract: A semiconductor device is provided having as an insulating oxide film a silicon oxide film containing a metal, such as iron or chromium, of an average concentration of 1.times.10.sup.16 atoms/cm.sup.3 to 1.times.10.sup.19 atoms/cm.sup.3 which can be readily trapped therein.
    Type: Grant
    Filed: January 22, 1988
    Date of Patent: June 6, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hachiro Hiratsuka, Yoshiaki Matsushita, Shintaro Yoshii
  • Patent number: 4805419
    Abstract: This invention relates to an absorption type heat exchanging apparatus having an evaporation unit, an absorption unit, a condensation unit and a regeneration unit. A diluted absorption liquid transfer pipe and a concentrated absorption liquid transfer pipe are installed between the absorption and regeneration units. A pump placed in one of these pipes is connected to a power take-off device which is placed in the other pipe and which is adapted to have rotative driving power imparted thereto by the absorption liquid in the pipe. Rotative driving power is imparted to the power take-off device by the energy based on the difference between the pressures in the regeneration and absorption units. This rotative driving power is transmitted to the pump. Thereby, the power to be provided to the pump from the outside is reduced.
    Type: Grant
    Filed: February 25, 1988
    Date of Patent: February 21, 1989
    Assignee: Hitachi Zosen Corporation
    Inventors: Tetsuro Furukawa, Kensuke Yoshikawa, Mitsuru Mizuuchi, Masaharu Furutera, Nobuharu Sakabata, Yoshiaki Matsushita, Tomoyoshi Muto, Tatsuhiko Umeda
  • Patent number: 4787997
    Abstract: An etching solution used for evaluating crystal defects in a silicon wafer is disclosed. The etching solution is characterized by consisting of acetic acid, hydrofluoric acid, nitric acid, silver nitrate, and copper nitrate, and is very advantageous in consideration of the operator's health, since it does not contain Cr.sup.6+. The etching solution has a sufficiently high etching rate and detection properties.
    Type: Grant
    Filed: March 2, 1988
    Date of Patent: November 29, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiko Saito, Yoshiaki Matsushita
  • Patent number: 4672821
    Abstract: An absorption-type heat pump includes an evaporator 1, an absorber 7, a regenerator 12, and a condenser 17. In the evaporator 1, water 4 as a refrigerant is flash-evaporated through a flash evaporating device 2. The water vapor 6 from the evaporator 1 is absorbed into an absorbent consisting of an aqueous lithium bromide solution in the absorber 7, so that a heat carrier fluid 8 is heated by the heat of absorption evolved within the absorber. In the regenerator 12, the diluted absorbent 9 received from the absorber 7 is heated with a heating fluid 13, whereby the absorbed water content of the absorbent 9 is evaporated. The concentrated absorbent 14 resulting from the step of regeneration is returned to the absorber 7, while the water vapor 16 evolved in the regenerator 12 is introduced into the condenser 17. The heat carrier fluid 8, which has been heated in the absorber 7, is passed through the condenser 17, being further heated by the heat of condensation within the condenser 17.
    Type: Grant
    Filed: November 21, 1985
    Date of Patent: June 16, 1987
    Assignee: Hitachi Zosen Corporation
    Inventors: Masaharu Furutera, Tetsuro Furukawa, Yoshiaki Matsushita, Kenji Nakauchi
  • Patent number: 4662191
    Abstract: An absorption refrigeration system includes an evaporator 1, an absorber 6, a regenerator 9, and a condenser 13. In the evaporator 1, water as a refrigerant is caused to evaporate by depriving a chill carrier fluid 4 of its heat. The water vapor 5 from the evaporator 1 is absorbed into an absorbent consisting of an aqueous lithium bromide solution in the absorber 6, heat being generated thereby. The regenerator 9 receives the diluted absorbent 7 from the absorber 6 and heat same with a heating fluid 11 to evaporate the absorbed water from the absorbent. The concentrated absorbent 10 resulting from the step of regeneration is returned to the absorber 6, while the water vapor 12 generated in the regenerator 9 is introduced into the condenser 13. A supply of condensing water 14 is sprayed into the condenser 13 for direct contact with the incoming water vapor 12 to condense the latter.
    Type: Grant
    Filed: November 21, 1985
    Date of Patent: May 5, 1987
    Assignee: Hitachi Zosen Corporation
    Inventors: Masaharu Furutera, Tetsuro Furukawa, Yoshiaki Matsushita
  • Patent number: 4645546
    Abstract: Disclosed is a silicon semiconductor substrate for a semiconductor integrated circuit such as LSI or VLSI. The silicon semiconductor substrate has an oxygen concentration ranging from 3.times.10.sup.17 cm.sup.-3 to 7.times.10.sup.17 cm.sup.-3 and a gettering layer on its backside. This gettering layer may comprise a nonsingle crystalline silicon layer such as polycrystalline silicon layer or amorphous silicon layer, or a layer having stacking fault density of more than 3.times.10.sup.4 cm.sup.-2.
    Type: Grant
    Filed: July 12, 1985
    Date of Patent: February 24, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Matsushita
  • Patent number: 4579601
    Abstract: A method for manufacturing a semiconductor device has the steps of: forming a first thin single-crystal semiconductor layer on a semiconductor substrate of one conductivity type which contains oxygen, the first thin single-crystal semiconductor layer having a higher resistivity than that of the semiconductor substrate and having the same conductivity type as that of the semiconductor substrate; ion-implanting an electrically inactive impurity in the first thin single-crystal semiconductor layer; forming a second thin single-crystal semiconductor layer on the first thin single-crystal semiconductor layer, the second thin single-crystal semiconductor layer having the same conductivity type as that of the semiconductor substrate and having a higher resistivity than that of the semiconductor substrate; performing annealing for not less than four hours at a temperature of 550.degree. C. to 900.degree. C.
    Type: Grant
    Filed: July 27, 1984
    Date of Patent: April 1, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Samata, Yoshiaki Matsushita
  • Patent number: 4500388
    Abstract: A monocrystalline semiconductor film is formed on an insulating film first by selectively forming at least one insulating film which has sides substantially perpendicular to <100> or <211>-axes, contiguous to a cubic crystal system monocrystalline semiconductor substrate. An amorphous film of a cubic crystal system semiconductor material is formed to cover an exposed surface of substrate and the insulating film. The amorphous semiconductor film is annealed under a condition such that the amorphous film is grown from the substrate by solid-phase epitaxial growth, thereby converting the amorphous film to a monocrystalline semiconductor film having a crystal lattice continuous to that of the substrate.
    Type: Grant
    Filed: November 29, 1982
    Date of Patent: February 19, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yamichi Ohmura, Yoshiaki Matsushita
  • Patent number: 4378269
    Abstract: A method of manufacturing a single crystal silicon rod by the pulling method which is characterized in that the intracrystal temperature of the growing single crystal silicon rod is reduced from 900.degree. to 500.degree. C. in less than 4 hours.
    Type: Grant
    Filed: June 24, 1981
    Date of Patent: March 29, 1983
    Assignee: VLSI Technology Research Association
    Inventors: Yoshiaki Matsushita, Shinichiro Takasu, Seigo Kishino
  • Patent number: 4376657
    Abstract: In a gettering method for processing semiconductor wafers a semiconductor wafer such as a silicon wafer is first annealed in a non-oxidizing atmosphere, for example, in a nitrogen atmosphere, at a temperature in the range of 950.degree. to 1,300.degree. C., preferably at 1,050.degree. C., for more than 10 minutes, for example for four (4) hours, to diffuse out oxygen near the surfaces of the semiconductor wafer. Then the semiconductor wafer is annealed at a temperature in the range of 600.degree. to 800.degree. C., for example at 650.degree. C., for more than one hour, preferably for 16 hours, to create in the interior of the semiconductor wafer microdefects of high density.
    Type: Grant
    Filed: December 5, 1980
    Date of Patent: March 15, 1983
    Assignee: VLSI Technology Research Association
    Inventors: Kazutoshi Nagasawa, Seigo Kishino, Yoshiaki Matsushita, Masaru Kanamori
  • Patent number: 4314595
    Abstract: A silicon single crystal wafer is subjected to two-stage heat treatment. In the first-stage it is heated at a temperature within the range of between 500.degree. C. and 1,000.degree. C. Subsequently the thus heated wafer is heated at a temperature higher than that at the first stage. Thus, a nondefective zone is formed in the surface region of the wafer, and the interior zone of the wafer becomes rich in micro defects capable of gettering impurities such as heavy metals.
    Type: Grant
    Filed: January 8, 1980
    Date of Patent: February 9, 1982
    Assignee: VLSI Technology Research Association
    Inventors: Kazuhiko Yamamoto, Yoshiaki Matsushita, Masaru Kanamori, Kazutoshi Nagasawa, Naotsugu Yoshihiro, Seigo Kishino
  • Patent number: 4193783
    Abstract: A method of treating a silicon single crystal ingot which comprises the steps of purposely producing lattice strains in a silicon single crystal ingot, annealing the ingot at high temperature, and etching off the surface of the annealed ingot, thereby suppressing the occurrence of lattice defects.
    Type: Grant
    Filed: June 15, 1978
    Date of Patent: March 18, 1980
    Assignee: VLSI Technology Research Association
    Inventor: Yoshiaki Matsushita