Patents by Inventor Yoshiaki Sato

Yoshiaki Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200154023
    Abstract: In order to provide a technique for improving precision of location estimation using a video, a location estimation device includes: a video processing unit that executes video processing including location estimation of an imaging unit, based on a plurality of feature points extracted from a video captured by the imaging unit and composed of a plurality of frames; and an imaging control unit that determines, on the basis of video-related information acquired in the video processing on a first frame belonging to a first group out of the plurality of frames, an exposure condition of the imaging unit in a second frame belonging to a second group different from the first group out of the plurality of frames.
    Type: Application
    Filed: July 27, 2017
    Publication date: May 14, 2020
    Applicant: NEC Corporation
    Inventors: Yoshiaki SATO, Noriyoshi HIROI, Gaku NAKANO
  • Publication number: 20200098679
    Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.
    Type: Application
    Filed: August 21, 2019
    Publication date: March 26, 2020
    Inventors: Yoshiaki SATO, Yoshinori MIYAKI, Junichi ARITA
  • Publication number: 20200083545
    Abstract: An electrochemical reaction unit includes a unit cell including an electrolyte layer, and a cathode and an anode which face each other in a first direction with the electrolyte layer intervening therebetween, and one or a plurality of structural members. The electrochemical reaction unit further includes a glass seal member which contains glass and is in contact with two members facing each other in the first direction, the two members being selected from the unit cell and the one or the plurality of structural members. The glass seal member contains a plurality of crystal grains each having a ratio of a vertical dimension in the first direction to a horizontal dimension in a second direction orthogonal to the first direction of 1.5 or more.
    Type: Application
    Filed: November 22, 2017
    Publication date: March 12, 2020
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Yoshiaki SATO, Ryoji TANIMURA, Kenta EGUCHI, Makoto KURIBAYASHI
  • Patent number: 10546173
    Abstract: An acquisition unit acquires a photographed image data which is photographed by a user at a first position in a space. The photographed image includes at least any of the multiple markers. An identification unit identifies the first position, on which user have photographed an image, based on the markers included in the photographed image. An informing unit identifies second position relative to the first position identified by the identification unit, and informs the user of the second position relative to the first position.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 28, 2020
    Assignee: NEC CORPORATION
    Inventors: Noriyoshi Hiroi, Yoshiaki Sato
  • Patent number: 10541216
    Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Keita Tsuchiya, Yoshiaki Sato, Shuuichi Kariyazaki, Norio Chujo, Masayoshi Yagyu, Yutaka Uematsu
  • Patent number: 10534048
    Abstract: A Q value of the RF irradiation coil is easily obtained in a state in which an object is disposed in an MRI apparatus, and an SAR is predicted with high accuracy. For this, an irradiation coil 14a irradiates an object 1 with a high frequency magnetic field pulse in a state in which the object 1 is disposed in an imaging space, and a transmitted voltage and a reflected voltage of the irradiation coil 14a are detected. A Q value of the irradiation coil in a state of the object 1 being disposed is obtained on the basis of the transmitted voltage and the reflected voltage. A specific absorption rate (SAR) in a case of executing an imaging pulse sequence on the object is predicted by using the Q value.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: January 14, 2020
    Assignee: HITACHI, LTD.
    Inventors: Koichi Arai, Takeshi Yatsuo, Yoshiaki Sato
  • Patent number: 10515890
    Abstract: A semiconductor device which provides improved reliability. The semiconductor device includes: a wiring substrate having a first surface and a second surface opposite to the first surface; a chip condenser built in the wiring substrate, having a first electrode and a second electrode; a first terminal and a second terminal disposed on the first surface; and a third terminal disposed on the second surface. The semiconductor device further includes: a first conduction path for coupling the first terminal and the third terminal; a second conduction path for coupling the first terminal and the first electrode; a third conduction path for coupling the third terminal and the first electrode; and a fourth conduction path for coupling the second terminal and the first electrode.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: December 24, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiaki Sato, Shuuichi Kariyazaki, Kazuyuki Nakagawa
  • Patent number: 10495844
    Abstract: Provided is a lens drive device that, using drive force from a voice coil motor, automatically carries out focusing by moving an autofocus movable unit with respect to an autofocus fixed unit in the direction of an optical axis. The lens drive unit is provided with a position detection unit that is disposed with an intervening space on the image formation side of the autofocus movable unit in the direction of the optical axis and that is for emitting light toward the autofocus movable unit, receiving reflected light that has been reflected by the autofocus movable unit, and detecting the position of the autofocus movable unit in the direction of the optical axis on the basis of the received light intensity. Part of the member displaced along with the autofocus movable unit functions as a reflective plate for reflecting light emitted from the position detection unit.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 3, 2019
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Yoshiaki Sato, Tomohiko Osaka, Noriyuki Kobayashi, Toshihiko Honma
  • Publication number: 20190290702
    Abstract: The present invention addresses the problem of providing a novel use of pluripotent stem cells (Muse cells) for medical purposes in regenerative medicine. The present invention provides a cell preparation and a pharmaceutical composition both for ameliorating and treating perinatal brain damage including learning disability and motor disability, each of the cell preparation and the pharmaceutical composition containing SSEA-3-positive pluripotent stem cells isolated from a mesenchymal tissue collected from a living body or cultured mesenchymal cells. The cell preparation according to the present invention relies on a mechanism that Muse cells are administered to a subject having the above-mentioned damage to cause the engraftment of the Muse cells in a damaged brain tissue, thereby ameliorating and treating the damage.
    Type: Application
    Filed: May 16, 2017
    Publication date: September 26, 2019
    Applicants: NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY, LIFE SCIENCE INSTITUTE, INC.
    Inventors: Yoshiaki Sato, Toshihiko Suzuki, Shinobu Shimizu, Masaaki Mizuno, Masahiro Hayakawa, Mari Dezawa
  • Patent number: 10415966
    Abstract: An identification unit obtains a plurality of photographic images including two or more markers. The makers are placed on a different object, respectively. The identification unit identifies, from the plurality of photographic images thus obtained, three-dimensional positions of the two or more markers. A generating unit transforms coordinate system of the plurality of photographic images into a common coordinate system. Relative positions of the two or more markers based on a specific location are indicated in the common coordinate system. The generating unit generates map data which associates the positions of the two or more markers.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: September 17, 2019
    Assignee: NEC CORPORATION
    Inventor: Yoshiaki Sato
  • Patent number: 10396044
    Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Keita Tsuchiya, Yoshiaki Sato, Shinji Baba
  • Publication number: 20190240262
    Abstract: The purpose of the present invention is to provide a novel medical use of pluripotent stem cells (Muse cells) in the regenerative medicine area. Provided are a cell preparation and a medicinal composition for ameliorating and treating chronic lung disease in newborns, said cell preparation and medicinal composition comprising SSEA-3-positive pluripotent stem cells isolated from a mesenchymal tissue in a living body or cultured mesenchymal cells. The cell preparation according to the present invention is based on a mechanism whereby the aforesaid disease is ameliorated and treated by administering Muse cells to a subject suffering from the disease and engrafting the cells in lung tissues.
    Type: Application
    Filed: August 3, 2017
    Publication date: August 8, 2019
    Applicants: National University Corporation Nagoya University, Life Science Institute, Inc., TOHOKU UNIVERSITY
    Inventors: Yoshiaki SATO, Toshihiko SUZUKI, Shinobu SHIMIZU, Masaaki MIZUNO, Masahiro HAYAKAWA, Mari DEZAWA
  • Patent number: 10361440
    Abstract: An electrochemical reaction unit containing a single cell including an electrolyte layer containing solid oxide, and a cathode and an anode which face each other in a first direction with the electrolyte layer intervening therebetween; a current collector disposed on a cathode side of the single cell and having a protrusion protruding toward the cathode; an electrically conductive coat covering a surface of the current collector; and an electrically conductive bonding layer bonding the cathode and the protrusion covered with the coat. In at least one section of the protrusion taken in parallel with the first direction, the protrusion covered with the coat has a covered portion covered with the bonding layer and an exposed portion exposed from the bonding layer and including a corner portion of the protrusion covered with the coat.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 23, 2019
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Yoshiaki Sato, Makoto Kuribayashi, Tomoki Murata, Takahiro Masumoto, Tomoo Tanaka
  • Publication number: 20190217143
    Abstract: A muscle training method includes the following steps that are repeated alternately to perform training of a muscle of a user: a pressuring and exercise step (S30, S50, S70, S90) of winding a belt around at least one of four limbs of the user and applying specific pressure thereto so as to restrict blood circulation of the muscle of the user without stopping the blood circulation, and asking the user to perform load-applied exercise to apply load of specific weight to the muscle of the user; and an exercise stopping step (S40, S60, S80, S100) of asking the user to stop the load-applied exercise while continuously applying the specific pressure to the user. The specific weight is set at a value smaller than maximum weight necessary for the user to exert maximum muscle force.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 18, 2019
    Inventor: Yoshiaki SATO
  • Publication number: 20190198462
    Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.
    Type: Application
    Filed: October 30, 2018
    Publication date: June 27, 2019
    Inventors: Kazuyuki NAKAGAWA, Keita TSUCHIYA, Yoshiaki SATO, Shuuichi KARIYAZAKI, Norio CHUJO, Masayoshi YAGYU, Yutaka UEMATSU
  • Patent number: 10325841
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Katsushi Terajima, Keita Tsuchiya, Yoshiaki Sato, Hiroyuki Uchida, Yuji Kayashima, Shuuichi Kariyazaki, Shinji Baba
  • Patent number: 10245458
    Abstract: A muscle training method includes the following steps that are repeated alternately to perform training of a muscle of a user: a pressuring and exercise step (S30, S50, S70, S90) of winding a belt around at least one of four limbs of the user and applying specific pressure thereto so as to restrict blood circulation of the muscle of the user without stopping the blood circulation, and asking the user to perform load-applied exercise to apply load of specific weight to the muscle of the user; and an exercise stopping step (S40, S60, S80, S100) of asking the user to stop the load-applied exercise while continuously applying the specific pressure to the user. The specific weight is set at a value smaller than maximum weight necessary for the user to exert maximum muscle force.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: April 2, 2019
    Assignee: KAATSU JAPAN CO., LTD.
    Inventor: Yoshiaki Sato
  • Publication number: 20180374788
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Application
    Filed: February 10, 2016
    Publication date: December 27, 2018
    Inventors: Kazuyuki NAKAGAWA, Katsushi TERAJIMA, Keita TSUCHIYA, Yoshiaki SATO, Hiroyuki UCHIDA, Yuji KAYASHIMA, Shuuichi KARIYAZAKI, Shinji BABA
  • Patent number: 10156615
    Abstract: Provided is a technique that enables accurate SAR management using power consumption by an object (Pobject) that was calculated based on accurately acquired Q-factors. For this purpose, the present invention calculates Q-factors of each channel of a high-frequency antenna using measurement results of amplitudes of forward waves and reflected waves of each high-frequency signal between three or more different frequencies. An existing SAR monitor in an MRI apparatus is used for the amplitude measurement. Also, the Q-factors are calculated based on a circuit coefficient to be acquired by fitting the measurement results to a predetermined circuit model. Then, the power consumption by an object (Pobject) is calculated using the calculated Q-factors in order to manage the SAR.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: December 18, 2018
    Assignee: HITACHI, LTD.
    Inventors: Hideta Habara, Yoshihisa Soutome, Masahiro Takizawa, Yoshiaki Sato
  • Patent number: 10135105
    Abstract: A differential transmission cable includes a pair of signal lines, an insulation covering the pair of signal lines, and a shielding tape that includes a conductor layer and an insulation layer formed on one surface of the conductor layer and is helically wound around the insulation. The diameter of the signal line is thinner than at least 30 AWG (American Wire Gauge), and differential characteristic impedance is not less than 80? and not more than 120?.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: November 20, 2018
    Assignee: HITACHI METALS, LTD.
    Inventors: Hiroshi Ishikawa, Takahiro Sugiyama, Mitsugu Takahashi, Yoshiaki Sato