Abstract: The invention aims at securely generating an internal supply voltage when turning on the power supply of internal circuits in a semiconductor integrated circuit where the operation voltage is low, and securely resetting the internal circuits. The voltage generator generates an internal supply voltage supplied to the internal circuits based on the reference voltage by using the external supply voltage supplied from the exterior. That is, the voltage generator forcibly supplies the external supply voltage as internal supply voltage when the power-on reset signal is activated. Therefore, when the external supply voltage is low at the time of turning-on of the power, and the voltage generator does not operate normally, the internal supply voltage can be securely generated following the external supply voltage so as to be supplied to the internal circuits.

Abstract: The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

Abstract: A drive power supply method for a semiconductor device is provided. The semiconductor device has an internal supply voltage generating circuit. First and second internal circuits are connected to the internal supply voltage generating circuit. Drive power is supplied to the first and second internal circuits from the internal supply voltage generating circuit. The second internal circuit operates in standby mode, power-down mode and active mode, so that the internal supply voltage is stably retained in the standby mode or power-down mode, and the consumed current is reduced.

Abstract: The adjustment control circuit activates the first adjustment signal that adjusts the characteristic of an internal circuit in response to an adjustment signal from the exterior. The ROM circuit activates the second adjustment signal that adjusts the characteristic of the internal circuit when information to adjust the characteristics of the internal circuits is programmed. The selecting circuit outputs either of the first or the second adjustment signal in response to a control signal. The characteristics of the internal circuits are adjusted in response to either the first or the second adjustment signal. Therefore, the second adjustment signal is masked by the selecting circuit selecting the first adjustment signal. That is, at this time, the information programmed in advance in the ROM circuit is invalidated. Further, where no information is programmed in the ROM circuit, the characteristics of the internal circuits can be adjusted without programming the ROM circuit.

Abstract: A method for controlling an internal supply voltage generating circuit reduces power consumption in an active mode. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to an internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. Then, at least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pose of the active mode. The first voltage-drop regulator is activated when the active pose is cancelled.

Abstract: A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.

Abstract: An input circuit for use in a semiconductor integrated circuit decreases a phase lag between a clock signal and an input signal. The input circuit includes a first amplifier that receives an external clock signal at a first input and a reference voltage signal at a second input, and generates an amplified clock signal, and a second amplifier that receives an external input signal at a first input and the reference voltage at a second input, and generates an amplified input signal. A latch circuit is connected to the first and second amplifiers and receives the amplified clock signal at its clock input and the amplified input signal at its data input. The first and second amplifiers receive a high voltage supply signal from a common a high potential power supply and a low voltage supply signal from a common low potential power supply.

Abstract: A semiconductor memory device comprises a plurality of memory cells for storing cell data. Word lines are connected to the memory cells. A first bit line includes a primary bit line connected to each memory cell and a secondary bit line. A first switching circuit is connected between the primary and secondary bit lines. A sense amplifier is connected to the secondary bit line. A second bit line is connected to the sense amplifier. A second switching circuit is connected between the second bit line and one of the primary and secondary bit lines.

Abstract: Improved method of laser induced photothermal displacement spectroscopy comprises the steps of applying pulsed laser light to the solution in a sample container, whereupon the light energy absorbed by the solution is converted to heat, with the resulting elastic wave displacing the wall of the sample container by vibrations, detecting the displacement by heterodyne interferometry, and measuring the absorption spectrum of the solution.

Abstract: A process for preparing a liquid MDI, which comprises adding, to MDI, a phospholine catalyst and a phosphorous acid ester of a specified formula and conducting a carbodiimidization reaction.

Abstract: A semiconductor memory device writes data to memory cells contained in the memory device in response to an enable signal supplied thereto. The memory device includes, a pair of bit lines connected to the memory cells, and a sense amplifier connected to the pair of bit lines to latch cell data read from the memory cells. The pair of bit lines couples to a data writing circuit, which writes data to the memory cells in response to the first enable signal. The memory device also includes a switching circuit connected to the sense amplifier, for disabling the sense amplifier in response to the first enable signal.

Abstract: A data transfer system including an exchange, wherein the exchange transfers data by sharing a plurality of channels by a time division multiplex mode. In this case, the exchange transfers the data by variably allocating respective time slots to be occupied by the respective channels. That is, it is possible to allot any line speed to any channel and therefore possible to mix signals with different data transfer speeds in the frames. This results in an exchange network with a high degree of freedom of transfer for the subscriber terminal equipment.

Abstract: A packet data switching system having packet switching equipment and a plurality of transfer control units cooperating with the packet switching equipment exchanging packet data to be transferred through the transfer control units. In the system each packet data is divided into packet frames each having the same frame length and all the packet frames are processed synchronously in each of the transfer control units. Each of the packet frames is composed of a header area and data area. The header area is used for indicating transfer control information, such as an address of a destination transfer control unit and a continuous transmission flag which denotes that the related packet frame should be exchanged to the same destination as that of the preceding packet frame.

Abstract: Disclosed is a semiconductor memory device. A read control signal is externally input in read mode, and a test mode signal is externally input in a mode for testing memory cells. Based on the input read control signal, plural pieces of read data read out from a plurality of memory cells are latched by a plurality of latch circuits. Output signals of the latch circuits are input to a data compressor, which checks if the output signals of the latch circuits are the same and outputs a resultant signal in a form of compressed data of one bit. The output signal of the data compressor is input to an output circuit, which outputs the output signal of the data compressor based on the input test mode signal. A preset circuit allows the latch circuits to latch different pieces of data based on the test mode signal and the read control signal.

Abstract: A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.

Abstract: A semiconductor memory device according to the invention includes a memory cell array (8) connected to a data bus through a first selector circuit (6), a second selector circuit (7) responsive to a first control signal (.phi. 0, .phi. X), a third selector circuit (8) responsive to a second control signal (.phi. 1 to .phi. 8), a row address buffer (17) responsive to activation of a row address strobe signal, an address fetching circuit (21) for instructing fetching of a column address every time of a specified number of toggled CAS signals, a column address buffer (19) responsive to a third control signal from the address fetching circuit (21), a nibble decoder (38) for generating the first and the second control signals, and a gate control circuit (39). A column address used to access a next memory cell is fetched during an activating period of the row address strobe signal after the column address is fetched.

Abstract: In a semiconductor integrated circuit for taking in an external power source voltage from outside the semiconductor chip, the external power source voltage is dropped by a voltage dropping unit installed inside the semiconductor chip and the external power source voltage in the semiconductor integrated circuit, as dropped is supplied as an internal power source voltage to the semiconductor chip and used as the internal power source voltage, a plurality of voltage dropping units are installed for each of a plurality of semiconductor circuit block installed inside the semiconductor chip, and the voltage fluctuation of an internal power source is effectively suppressed in the event that a circuit consuming a very high current is operated.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a plurality of word lines and bit lines connected to the memory cells, a data bus for carrying data to be written in and/or read out from a selected memory cell, an addressing circuit for selecting one of the word lines and bit lines, an input buffer for outputting the electric signal indicative of the data to be written on the data bus, a current-mirror amplifier connected to the data bus for amplifying the electric signals that are read out from the memory cell on the data bus, and a limiter circuit connected to the data bus for limiting a voltage swing of the electric signals on the data bus.

Abstract: A tap having a main body having a crest, a heel, and an outer circumference is disclosed. The tap main body has a male screw part at the crest side. At this male screw part, a plurality of grooves opening to the crest and the outer circumference of tap main body is formed. A tap main body has a cutting edge at each ridge part defined by a wall of said plurality of grooves and an outer circumference of a male screw part. These cutting edges each have a crest part and a heel part. The crest part of at least one cutting edge has an axial rake angle which differs from an axial rake angle of the crest part of another cutting edge.

Abstract: A current mirror amplifier circuit includes a differential amplifier circuit having first and second nodes for differentially amplifying a pair of complementary input signals in an activation mode. A current mirror circuit is coupled between a first power source and the first and second nodes of the differential amplifier circuit. A switching circuit is coupled between the differential amplifier circuit and a second power source which supplies a second voltage lower than a first voltage supplied by the first power source for switching a mode of the differential amplifier circuit from a standby mode to the activation mode in response to an activation signal. A circuit is coupled between the first power source and the first and second nodes of the differential amplifier circuit for pulling up potentials of the first and second nodes during the standby mode. This circuit is deactivated after the differential amplifier circuit is switched from the standby mode to the activation mode.