Abstract: A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

Abstract: The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

Abstract: There is disclosed a liquid crystal display apparatus including a main body and a swivel mechanism, where the main body is capable of smoothly swiveling. A countersunk hole is formed in a bottom plate member as follows: When a through-hole for inserting a screw is formed in a metal sheet to be a bottom plate member, there is also concurrently formed an accommodating hole for accommodating flow of the material forming the metal sheet upon plastic forming or pressing which is performed subsequently for forming a countersink, and then the countersink is formed at an open end of the through-hole by pressing. It is preferable that a plurality of the accommodating holes are formed around the through-hole.

Abstract: A liquid crystal display apparatus including a tilt mechanism, which is capable of preventing an inadvertent insertion of a finger of a user in a groove of a bracket of the tilt mechanism even while a cover for concealing the bracket is removed, wherein provided is a washer-like member or inadvertent-insertion preventer which has a through-hole or perforated portion through which a pawl formed in a mainbody bracket or one of two brackets is inserted, and is attached to the pawl at a position to contact a stand bracket or the other of the two brackets, by inserting the pawl through the through-hole. The washer-like member is preferably made of a plastic and sandwiched between the two brackets.

Abstract: A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

Abstract: The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor Substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second Semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

Abstract: An IC chip is provided with a wireless unit for inputting and outputting data by wireless communication, in addition to a logic section, so that the IC chip no longer needs I/O pads, leaving only power supply and ground pads. IC chips can input and output data with one another by wireless communications, which makes it possible to significantly improve the spacing relationships of various chips on a singular or even plurality of substrates.

Abstract: It is intended to provide a semiconductor integrated circuit device permitting reading of information specific to chips within the mounted chips while restraining the increase in the total number of terminals of the package and enabling the area of circuits required for reading information specific to chips to be made smaller than that according to the prior art, and a control method therefor. The same terminal is used as the external terminal to which the pulse signals are inputted and the external terminal from which the chip-specific information is outputted. Also, the external terminal for inputting/outputting required power supply in the normal operation mode and the external terminal for reading chip-specific information in the information reading mode are used in common. The increase in the number of external terminals can be thereby restrained. Moreover, the counter unit is shared between functional circuits and the comparative decision unit. This can serve to restrain the increase in chip area.

Abstract: The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

Abstract: It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k?1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

Abstract: It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

Abstract: There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal SWS2. In this case, the changeover is made so that a select signal S2 outputted from an internal circuit 40 is inputted to a predetermined memory terminal of the memory chip CC2. The select signal S2 is inputted to the corresponding predetermined memory terminal of the memory chip CC2, and thereby, the memory chip CC2 is activated, and set to a state capable of inputting and outputting control signals 21 to 25. The control signals 21 to 25 are assigned to control terminals P21 to P27 after being hanged by the select circuit 27 in signal sequence corresponding to terminal array sequence of memory terminals 21a to 27a of the memory chip CC2.

Abstract: In the case that a refresh operation is carried out which is independent from an external access operation, both a data access method of a semiconductor memory device, and a semiconductor memory device are provided by which time suitable of each of these external access operation and refresh operation is set. While a time-measuring start signal “SIN” is entered into a path switching means, the path switching means is connected to either a first timer section or a second timer section under control of an external-access-operation-start-request signal REQ(O) and a refresh-operation-start-request signal REQ(I). Both the first and second timer sections measure both time “?O” and time “?I” to output a time-measuring stop signal “SOUT.” The measuring time “?O” corresponds to differential amplification time of a bit line pair when the external access operation is carried out, whereas the measuring time “?I” corresponds to differential amplification time when the refresh operation is carried out.

Abstract: A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal ?CPR. The signal ?CPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

Abstract: A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.

Abstract: There is provided a semiconductor memory device and a redundancy judging method which can reduce current consumption when a static-type redundancy judging operation is performed. In case absence of substitute to auxiliary memory cells is set, a non-redundancy setting signal Jdg is set in high logic level and the comparing unit 3 is inactivated and has an operation thereof stopped. Logic fixing unit 5 is connected to respective comparison results E0-n. The logic fixing unit 5 is activated in response to the non-redundancy setting signal Jdg of high logic level and fixes the respective comparison results E0-n to a predetermined logic level. The predetermined logic level is a value which indicates the discordance of the comparison results E0-n and hence, logic composing unit 7 judges that address information and redundancy address information discord with each other.

Abstract: A semiconductor memory device having a driver transistor for the supply of electric power is provided, which can diminish leakage current during inactivation while ensuring sufficient power supply capability for a sense amplifier during activation. Gate width is provided at every two bit line pair pitches perpendicularly to a bit line direction, and a supply voltage VDD and a reference voltage VSS are fed to PMOS transistors SP0, SP0_ to SP3, sP3_ and NMOS transistors SN0, SN0_ to SN3, SN3_. In driver-dedicated PMOS transistors P1, P2, and NMOS transistors N1, N2, gate width is adjusted using the length of two bit line pair pitches as a maximum value, while gate length is adjusted using an adjusting region &Dgr;L, whereby there can be obtained driver-dedicated MOS transistors P1, P2, N1, and N2 in an appropriately adjusted state with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and diminishing a tailing current.

Abstract: A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

Abstract: There is provided an inventive semiconductor memory device and control method thereof capable of preventing shift operation to deactivated state and data access due to transition of address signals from occurring concurrently without accompanying delay of access time, thereby to prevent data-holding characteristic of memory cell from deteriorating. A column selecting circuit 16 is deactivated based on an input signal EXBn outputted to a glitch canceller 20 prior to precharge signal PRE so as to prevent selection of a column selecting signal CLn and deactivation of a word line WL from occurring concurrently. This manner substitutes for taking delay time &tgr;D that is to be added to signals CAGn from which glitch noises due to transition of address CAn are eliminated.

Abstract: The present invention relates to an apparatus and method for reducing the frequency with which memory is accessed in graphic printing or the like. If a CPU 100 reads image data from a buffer block where data has not been written, a memory controller 12 does not read the image data from a image buffer 140, but sends back initializing data stored beforehand. If image data is going to be written for the first time in a buffer block, the memory controller 12 stores and manages this image data, first writes the initializing data in this buffer block, and thereafter writes the image data. If a read request or a write request occurs to a buffer block where data has already been written, the memory controller 12 reads or writes data as requested.