Patents by Inventor Yoshiharu Takada

Yoshiharu Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998437
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·?m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pr
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya Ohguro, Tatsuya Nishiwaki, Hideharu Kojima, Yoshiharu Takada, Kikuo Aida, Kentaro Ichinoseki, Kohei Oasa, Shingo Sato
  • Publication number: 20200402946
    Abstract: A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.
    Type: Application
    Filed: March 2, 2020
    Publication date: December 24, 2020
    Inventor: Yoshiharu TAKADA
  • Patent number: 10825756
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, and a die pad. The die pad has a first surface. The semiconductor chip is bonded on the first surface using a paste including a metal particle. A concave structure is provided in the first surface. The concave structure is positioned directly under each of a plurality of sides of the semiconductor chip and extends along each of the plurality of sides.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 3, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hideharu Kojima, Yoshiharu Takada
  • Patent number: 10784165
    Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 22, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shingo Masuko, Kazuo Fujimura, Yoshiharu Takada, Ichiro Mizushima
  • Publication number: 20200152785
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pro
    Type: Application
    Filed: August 5, 2019
    Publication date: May 14, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya OHGURO, Tatsuya NISHIWAKI, Hideharu KOJIMA, Yoshiharu TAKADA, Kikuo AIDA, Kentaro ICHINOSEKI, Kohei OASA, Shingo SATO
  • Publication number: 20200075464
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, and a die pad. The die pad has a first surface. The semiconductor chip is bonded on the first surface using a paste including a metal particle. A concave structure is provided in the first surface. The concave structure is positioned directly under each of a plurality of sides of the semiconductor chip and extends along each of the plurality of sides.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 5, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELETRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hideharu KOJIMA, Yoshiharu Takada
  • Publication number: 20190267288
    Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a semiconductor layer, and a lower layer. The semiconductor layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.
    Type: Application
    Filed: March 12, 2018
    Publication date: August 29, 2019
    Inventors: Shingo Masuko, Kazuo Fujimura, Yoshiharu Takada, Ichiro Mizushima
  • Patent number: 10074736
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 9953894
    Abstract: A semiconductor device including: a semiconductor element, a substrate having a first surface on which the semiconductor element is provided, and a second surface located opposite the first surface, a metal species provided on the second surface, and a plated metal portion provided at least in part on the second surface on the metal species. The semiconductor device further includes a first region where the plated metal portion is provided and a second region where the plated metal portion is not provided are alternately arranged at a peripheral portion of the second surface.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 24, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shingo Masuko, Yoshiharu Takada, Kazuo Fujimura
  • Publication number: 20180082918
    Abstract: A semiconductor device including: a semiconductor element, a substrate having a first surface on which the semiconductor element is provided, and a second surface located opposite the first surface, a metal species provided on the second surface, and a plated metal portion provided at least in part on the second surface on the metal species. The semiconductor device further includes a first region where the plated metal portion is provided and a second region where the plated metal portion is not provided are alternately arranged at a peripheral portion of the second surface.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 22, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shingo MASUKO, Yoshiharu TAKADA, Kazuo FUJIMURA
  • Publication number: 20160268408
    Abstract: A semiconductor device includes a first compound semiconductor layer on a substrate, a second compound semiconductor layer on the first compound semiconductor layer which has a band gap greater than the band gap of the first compound semiconductor layer, and a gate electrode on the second compound semiconductor layer. The gate length of the gate electrode is more twice as great as the thickness of the first compound semiconductor layer, and is equal to or smaller than five times as great as the thickness of the first compound semiconductor layer.
    Type: Application
    Filed: August 31, 2015
    Publication date: September 15, 2016
    Inventors: Kohei OASA, Yoshiharu TAKADA, Akira YOSHIOKA, Yasuhiro ISOBE, Hung HUNG
  • Publication number: 20160268410
    Abstract: A semiconductor device includes: a substrate; a first compound semiconductor layer provided on the substrate; a second compound semiconductor layer provided on the first compound semiconductor layer and having a band gap larger than that of the first compound semiconductor layer; a first element isolation region provided in the first compound semiconductor layer and the second compound semiconductor layer; and a first electrode and a second electrode which are electrically connected to a first conductive region formed from the first and second compound semiconductor layers arranged outside the first element isolation region.
    Type: Application
    Filed: September 1, 2015
    Publication date: September 15, 2016
    Inventors: Takashi Onizawa, Yoshiharu Takada
  • Patent number: 9419119
    Abstract: A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiharu Takada, Takeshi Shibata
  • Publication number: 20160218067
    Abstract: A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, and a protection layer, comprising carbon, covering a side surface of the nitride semiconductor layer.
    Type: Application
    Filed: August 31, 2015
    Publication date: July 28, 2016
    Inventors: Shingo MASUKO, Yoshiharu TAKADA, Takashi ONIZAWA, Yasuhiro ISOBE, Kohei OASA
  • Publication number: 20160211225
    Abstract: A semiconductor device includes a substrate, and a nitride semiconductor layer provided on the substrate. An opening is provided through the nitride semiconductor layer, and a portion of the opening extends inwardly of a side surface of the substrate and beneath the nitride semiconductor layer.
    Type: Application
    Filed: August 20, 2015
    Publication date: July 21, 2016
    Inventors: Shingo MASUKO, Yoshiharu TAKADA
  • Publication number: 20160079066
    Abstract: A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode.
    Type: Application
    Filed: February 26, 2015
    Publication date: March 17, 2016
    Inventors: Yoshiharu TAKADA, Takeshi SHIBATA
  • Publication number: 20160079120
    Abstract: A semiconductor device includes a semiconductor substrate that has a first surface and a second surface opposite to the first surface, and has a groove or trench extending from the first surface toward the second surface, a bottom of the groove being situated between the first surface and the second surface, and a gallium nitride-containing layer on the first surface of the semiconductor substrate having a trench tapering inwardly along a direction toward the first surface of the semiconductor substrate and connected to the groove.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Inventors: Shingo MASUKO, Yoshiharu TAKADA, Yasuhiro ISOBE
  • Patent number: 9287368
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Akira Yoshioka, Yoshiharu Takada
  • Publication number: 20160013303
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu TAKADA
  • Patent number: 9171807
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada