Patents by Inventor Yoshiharu Takada

Yoshiharu Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160211225
    Abstract: A semiconductor device includes a substrate, and a nitride semiconductor layer provided on the substrate. An opening is provided through the nitride semiconductor layer, and a portion of the opening extends inwardly of a side surface of the substrate and beneath the nitride semiconductor layer.
    Type: Application
    Filed: August 20, 2015
    Publication date: July 21, 2016
    Inventors: Shingo MASUKO, Yoshiharu TAKADA
  • Publication number: 20160079066
    Abstract: A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode.
    Type: Application
    Filed: February 26, 2015
    Publication date: March 17, 2016
    Inventors: Yoshiharu TAKADA, Takeshi SHIBATA
  • Publication number: 20160079120
    Abstract: A semiconductor device includes a semiconductor substrate that has a first surface and a second surface opposite to the first surface, and has a groove or trench extending from the first surface toward the second surface, a bottom of the groove being situated between the first surface and the second surface, and a gallium nitride-containing layer on the first surface of the semiconductor substrate having a trench tapering inwardly along a direction toward the first surface of the semiconductor substrate and connected to the groove.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Inventors: Shingo MASUKO, Yoshiharu TAKADA, Yasuhiro ISOBE
  • Patent number: 9287368
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Akira Yoshioka, Yoshiharu Takada
  • Publication number: 20160013303
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu TAKADA
  • Patent number: 9171807
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Publication number: 20150126011
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiko KURAGUCHI, Akira Yoshioka, Yoshiharu Takada
  • Patent number: 8969917
    Abstract: According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mayumi Morizuka, Yoshiharu Takada
  • Patent number: 8963203
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Akira Yoshioka, Yoshiharu Takada
  • Patent number: 8816388
    Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 8723234
    Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiharu Takada, Kentaro Ikeda
  • Publication number: 20140097449
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Application
    Filed: September 13, 2013
    Publication date: April 10, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu TAKADA
  • Publication number: 20130256753
    Abstract: According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.
    Type: Application
    Filed: March 7, 2013
    Publication date: October 3, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mayumi MORIZUKA, Yoshiharu Takada
  • Publication number: 20130248873
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiko KURAGUCHI, Akira Yoshioka, Yoshiharu Takada
  • Patent number: 8525274
    Abstract: A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Publication number: 20130062625
    Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.
    Type: Application
    Filed: February 29, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu TAKADA
  • Publication number: 20120228632
    Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.
    Type: Application
    Filed: September 7, 2011
    Publication date: September 13, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiharu Takada, Kentaro Ikeda
  • Patent number: 8169035
    Abstract: A semiconductor device, including: a semiconductor substrate; a plurality of unit cells connected in parallel with each other, each unit cell including a plurality of electric field effect transistors formed on the semiconductor substrate; a plurality of gate bus wirings each configured to connect each of the gate electrodes of the transistors constituting the unit cell; a plurality of gate pad electrodes having a multi-layered structure of conductive layers, each of the gate pad electrodes connected to the gate bus wiring; and a resistive element configured to connect adjacent gate pad electrodes and formed along at least one side of an outer peripheral portion of the gate pad electrode, and formed of at least one conductive layer of the conductive layers constituting the gate pad electrode.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Publication number: 20120043591
    Abstract: A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode.
    Type: Application
    Filed: March 17, 2011
    Publication date: February 23, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu TAKADA
  • Publication number: 20110254235
    Abstract: A laminated-type metal gasket material plate includes a metal plate having two sides, a rubber layer, a layer of a surface preparation agent free from hexavalent chromium, and an adhesive layer. The layer of the surface preparation agent is coated on at least one side of the plate. The adhesive layer attaches the rubber layer and is provided on the layer of the surface preparation agent. Both the adhesive layer and the rubber layer contain a rust-resistant pigment.
    Type: Application
    Filed: June 10, 2011
    Publication date: October 20, 2011
    Inventors: Tsunehiko Abe, Tomokazu Nakanishi, Shingo Watanabe, Yoshiharu Takada, Ichiro Goto, Shinsuke Mochizuki, Kenji Okubo, Yasuaki Nagai