Patents by Inventor Yoshiharu Takada
Yoshiharu Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9419119Abstract: A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode.Type: GrantFiled: February 26, 2015Date of Patent: August 16, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiharu Takada, Takeshi Shibata
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Publication number: 20160218067Abstract: A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, and a protection layer, comprising carbon, covering a side surface of the nitride semiconductor layer.Type: ApplicationFiled: August 31, 2015Publication date: July 28, 2016Inventors: Shingo MASUKO, Yoshiharu TAKADA, Takashi ONIZAWA, Yasuhiro ISOBE, Kohei OASA
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Publication number: 20160211225Abstract: A semiconductor device includes a substrate, and a nitride semiconductor layer provided on the substrate. An opening is provided through the nitride semiconductor layer, and a portion of the opening extends inwardly of a side surface of the substrate and beneath the nitride semiconductor layer.Type: ApplicationFiled: August 20, 2015Publication date: July 21, 2016Inventors: Shingo MASUKO, Yoshiharu TAKADA
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Publication number: 20160079066Abstract: A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode.Type: ApplicationFiled: February 26, 2015Publication date: March 17, 2016Inventors: Yoshiharu TAKADA, Takeshi SHIBATA
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Publication number: 20160079120Abstract: A semiconductor device includes a semiconductor substrate that has a first surface and a second surface opposite to the first surface, and has a groove or trench extending from the first surface toward the second surface, a bottom of the groove being situated between the first surface and the second surface, and a gallium nitride-containing layer on the first surface of the semiconductor substrate having a trench tapering inwardly along a direction toward the first surface of the semiconductor substrate and connected to the groove.Type: ApplicationFiled: March 3, 2015Publication date: March 17, 2016Inventors: Shingo MASUKO, Yoshiharu TAKADA, Yasuhiro ISOBE
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Patent number: 9287368Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.Type: GrantFiled: January 9, 2015Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Kuraguchi, Akira Yoshioka, Yoshiharu Takada
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Publication number: 20160013303Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.Type: ApplicationFiled: September 22, 2015Publication date: January 14, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Yoshiharu TAKADA
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Patent number: 9171807Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.Type: GrantFiled: September 13, 2013Date of Patent: October 27, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiharu Takada
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Publication number: 20150126011Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.Type: ApplicationFiled: January 9, 2015Publication date: May 7, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masahiko KURAGUCHI, Akira Yoshioka, Yoshiharu Takada
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Patent number: 8969917Abstract: According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.Type: GrantFiled: March 7, 2013Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Mayumi Morizuka, Yoshiharu Takada
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Patent number: 8963203Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.Type: GrantFiled: March 11, 2013Date of Patent: February 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Kuraguchi, Akira Yoshioka, Yoshiharu Takada
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Patent number: 8816388Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.Type: GrantFiled: February 29, 2012Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiharu Takada
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Patent number: 8723234Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.Type: GrantFiled: September 7, 2011Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiharu Takada, Kentaro Ikeda
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Publication number: 20140097449Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.Type: ApplicationFiled: September 13, 2013Publication date: April 10, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Yoshiharu TAKADA
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Publication number: 20130256753Abstract: According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.Type: ApplicationFiled: March 7, 2013Publication date: October 3, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Mayumi MORIZUKA, Yoshiharu Takada
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Publication number: 20130248873Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.Type: ApplicationFiled: March 11, 2013Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Masahiko KURAGUCHI, Akira Yoshioka, Yoshiharu Takada
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Patent number: 8525274Abstract: A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode.Type: GrantFiled: March 17, 2011Date of Patent: September 3, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiharu Takada
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Publication number: 20130062625Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.Type: ApplicationFiled: February 29, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Yoshiharu TAKADA
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Publication number: 20120228632Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.Type: ApplicationFiled: September 7, 2011Publication date: September 13, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiharu Takada, Kentaro Ikeda
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Patent number: 8169035Abstract: A semiconductor device, including: a semiconductor substrate; a plurality of unit cells connected in parallel with each other, each unit cell including a plurality of electric field effect transistors formed on the semiconductor substrate; a plurality of gate bus wirings each configured to connect each of the gate electrodes of the transistors constituting the unit cell; a plurality of gate pad electrodes having a multi-layered structure of conductive layers, each of the gate pad electrodes connected to the gate bus wiring; and a resistive element configured to connect adjacent gate pad electrodes and formed along at least one side of an outer peripheral portion of the gate pad electrode, and formed of at least one conductive layer of the conductive layers constituting the gate pad electrode.Type: GrantFiled: September 17, 2009Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiharu Takada