Patents by Inventor Yoshihide Iwazaki
Yoshihide Iwazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100294342Abstract: A solar cell module 1 includes a plurality of solar cells 30. Each of the plurality of solar cells 30 is disposed on a corresponding one of a plurality of pad sections in such a manner that the each of the plurality of solar cells 30 is electrically connected to the corresponding one of the plurality of pad sections. The each of the plurality of solar cells 30 is electrically connected to a corresponding inner lead section 120. A cathode section 114 and an anode section 116 feed an electric current generated by the plurality of solar cells 30. A metal lead frame is provided such that the plurality of pad sections, the inner lead sections 120, the cathode section 114 and the anode section 116 are provided therein as a part of the lead frame itself. This configuration enables the solar cell module 1 to endure against bending stress and to be curved. As a result, it is possible to provide a solar cell module which can be disposed along a curved surface of an electronics device.Type: ApplicationFiled: May 20, 2010Publication date: November 25, 2010Inventors: Hiroyuki Nakanishi, Kohji Miyata, Yoshihide Iwazaki, Seiji Ishihara, Masato Yokobayashi, Etsuko Ishizuka, Kiyoharu Shimano, Katsunobu Mori
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Publication number: 20100147376Abstract: A solar battery device includes: a substrate; a plurality of solar cells on the substrate; and a surface protector on the solar cell, so as to protect a surface of the solar battery device. The surface protector has an incident surface to which light enters, and which is subjected to an anti-reflection process for preventing reflection of the light, thereby to improve power generation efficiency. The anti-reflection process for examples gives the surface protector a saw-tooth-like shape. The surface protector is made of a synthetic resin. In this way, the present invention provides a solar battery device in which reduction in the power generation efficiency due to the surface protector or the like on the surface thereof is prevented, and which has excellent transportability and applicability to portable devices.Type: ApplicationFiled: December 8, 2009Publication date: June 17, 2010Inventors: Yoshihide Iwazaki, Kohji Miyata, Shohnosuke Ueno
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Publication number: 20100101626Abstract: A solar battery apparatus 10 has a plurality of solar battery cells 3 and electrode terminals 4, other than common electrode terminals, for making an electrical connection (i) between each of the solar battery cells 3 and another or (ii) between the solar battery cell 3 and an external apparatus, the solar battery apparatus 10 including: metal wires 5 for making an electrical connection between the solar battery cell 3 and the electrode terminals 4 in a plurality of places on the solar battery cell 3, whereby a decrease in power generation capacity of the solar battery cell 3 is prevented even if the solar battery cell 3 is ruptured by a physical force. This makes it possible to provide a solar battery apparatus in which a decrease in power generation capacity of a solar battery cell can be prevented even if the solar battery cell is ruptured by a physical force.Type: ApplicationFiled: October 22, 2009Publication date: April 29, 2010Inventors: Yoshihide Iwazaki, Hiroyuki Nakanishi, Kohji Miyata, Masahiro Okita, Hideya Takakura
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Patent number: 7445958Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.Type: GrantFiled: June 26, 2006Date of Patent: November 4, 2008Assignee: Sharp Kabushiki KaishaInventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20080105555Abstract: An object of the present invention is to provide a face-down type jet plating device in which deterioration in plating quality due to minute solid foreign matters derived from a black film etc. is prevented without impairing operativity. The plating device is designed such that a partition (7) is provided between a semiconductor wafer (1) and an anode (5) so that the anode (5) and the semiconductor wafer (7) are separated from each other and a plating tank (100) is divided into a substrate-to-be-plated chamber and an anode chamber.Type: ApplicationFiled: December 8, 2005Publication date: May 8, 2008Inventor: Yoshihide Iwazaki
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Publication number: 20060237848Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.Type: ApplicationFiled: June 26, 2006Publication date: October 26, 2006Inventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20060226018Abstract: A plating apparatus according to the present invention is provided with a plating tank 100 in which an anode electrode 5 is provided, the plating apparatus performing the plating by (i) streaming a plating solution and an electrolytic liquid into the plating tank 100, (ii) emitting a jet of the plating solution to the plating-target face W of the semiconductor wafer 1 from the underneath of the semiconductor wafer 1, and (iii) streaming the electrolytic liquid to the anode electrode 5 while electrically conducting between the semiconductor wafer 1 and the anode electrode 5, the plating tank including a partition in between the semiconductor wafer 1 and the anode electrode 5, and the partition (i) separating the semiconductor wafer 1 and the anode electrode 5 and (ii) dividing the plating tank 100 into a plating-target substrate room and an anode electrode room.Type: ApplicationFiled: April 6, 2006Publication date: October 12, 2006Applicant: Sharp Kabushiki KaishaInventor: Yoshihide Iwazaki
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Patent number: 7091616Abstract: A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.Type: GrantFiled: June 7, 2002Date of Patent: August 15, 2006Assignee: Sharp Kabushiki KaishaInventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20050194686Abstract: A semiconductor device according to the present invention comprises an electrode pad electrically conducted to an electric circuit formed on an element-formed surface of a silicon wafer; a wiring pattern re-wired by being electrically conducted to the electrode pad; and an oxide film formed on a surface of the wiring pattern, the oxide film being formed by subjecting the wiring pattern to oxidization. With the provision of oxide film, the semiconductor device prevents a decrease in reliability in terms of electric characteristic or the like, and also achieves reduction in fabrication cost compared to a conventional semiconductor device.Type: ApplicationFiled: March 7, 2005Publication date: September 8, 2005Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihide Iwazaki, Shinji Suminoe, Katsunobu Mori
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Patent number: 6940175Abstract: A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin.Type: GrantFiled: June 7, 2002Date of Patent: September 6, 2005Assignee: Sharp Kabushiki KaishaInventors: Yoshihide Iwazaki, Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori
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Publication number: 20050104165Abstract: A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.Type: ApplicationFiled: December 29, 2004Publication date: May 19, 2005Applicant: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Yoshihide Iwazaki, Shinji Suminoe
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Patent number: 6838748Abstract: A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.Type: GrantFiled: May 9, 2003Date of Patent: January 4, 2005Assignee: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Yoshihide Iwazaki, Shinji Suminoe
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Patent number: 6831002Abstract: A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.Type: GrantFiled: September 13, 2002Date of Patent: December 14, 2004Assignee: Sharp Kabushiki KaishaInventors: Yoshihide Iwazaki, Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Takamasa Tanaka, Katsunobu Mori
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Publication number: 20030218257Abstract: A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.Type: ApplicationFiled: May 9, 2003Publication date: November 27, 2003Inventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Yoshihide Iwazaki, Shinji Suminoe
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Publication number: 20030134509Abstract: A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.Type: ApplicationFiled: September 13, 2002Publication date: July 17, 2003Inventors: Yoshihide Iwazaki, Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Takamasa Tanaka, Katsunobu Mori
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Patent number: 6558791Abstract: A heat-resistant adhesive is provided for use in an adhesive member for the fabrication of a semiconductor package by bonding a semiconductor chip to a lead frame with the adhesive member and sealing at least the semiconductor chip and a bonded part between the semiconductor chip and the lead frame with a sealant. The adhesive has a coming-out length of not more than 2 mm and a water absorption rate of not more than 3 wt. %. Preferably, the adhesive has a glass transition point of at least 200° C.Type: GrantFiled: April 10, 2001Date of Patent: May 6, 2003Assignee: Hitachi Chemical CompanyInventors: Hidekazu Matsuura, Yoshihide Iwazaki, Naoto Ohta
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Publication number: 20030025173Abstract: A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.Type: ApplicationFiled: June 7, 2002Publication date: February 6, 2003Inventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20020190392Abstract: A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin.Type: ApplicationFiled: June 7, 2002Publication date: December 19, 2002Inventors: Yoshihide Iwazaki, Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori
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Patent number: 6372080Abstract: A heat-resistant adhesive is provided for use in an adhesive member for the fabrication of a semiconductor package by bonding a semiconductor chip to a lead frame with the adhesive member and sealing at least the semiconductor chip and a bonded part between the semiconductor chip and the lead frame with a sealant. The adhesive has a coming-out length of not more than 2 mm and a water absorption rate of not more than 3 wt. %. Preferably, the adhesive has a glass transition point of at least 200° C.Type: GrantFiled: October 13, 1995Date of Patent: April 16, 2002Assignee: Hitachi Chemical Company, LtdInventors: Hidekazu Matsuura, Yoshihide Iwazaki, Naoto Ohta
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Publication number: 20010015484Abstract: A heat-resistant adhesive is provided for use in an adhesive member for the fabrication of a semiconductor package by bonding a semiconductor chip to a lead frame with the adhesive member and sealing at least the semiconductor chip and a bonded part between the semiconductor chip and the lead frame with a sealant. The adhesive has a coming-out length of not more than 2 mm and a water absorption rate of not more than 3 wt. %. Preferably, the adhesive has a glass transition point of at least 200° C.Type: ApplicationFiled: April 10, 2001Publication date: August 23, 2001Inventors: Hidekazu Matsuura, Yoshihide Iwazaki, Naoto Ohta