Abstract: An amplifier which performs the function of switching on and off its output signal includes an inverted Darlington circuit made up of an input transistor and an output transistor, a first switching circuit connected across the base and the emitter of the output transistor, and a second switching circuit connected between the emitter of the input transistor and the collector of the output transistor. Amplifier also includes means for opening the first switching circuit and closing the second switching circuit to send out an output signal, and for closing the first switching circuit and opening the second switching circuit to stop the output signal. The input and output transistors may be fabricated using vipolar or MOSFET technology because current of a small magnitude flows through the switching circuits, the switching circuits can be formed from elements that are small in size and which have small parasitic capacitance.

Abstract: In a digital circuitry apparatus in which clock distribution can be performed with high accuracy even in the case where variations in delay time are caused by variations in the apparatus operating condition, programmed input data set to delay circuits are corrected by a circuit portion for measuring the delay time of a phase shifting adjustment delay circuit with respect to variations in delay time caused by variations in the apparatus operating condition, a first arithmetic operation circuit for calculating the rate of variation on the basis of measured values, and a second arithmetic operation circuit for calculating the quantity of variation on the basis of the rate of variation.

Abstract: In a digital circuitry apparatus in which clock distribution can be performed with high accuracy even in the case where variations in delay time are caused by variations in the apparatus operating condition, programmed input data set to delay circuits are corrected by a circuit portion for measuring the delay time of a phase shifting adjustment delay circuit with respect to variations in delay time caused by variations in the apparatus operating condition, a first arithmetic operation circuit for calculating the rate of variation on the basis of measured values, and a second arithmetic operation circuit for calculating the quantity of variation on the basis of the rate of variation.

Abstract: A distributed timing signal generator as a component of a per-pin architecture tester is disclosed. Start control circuits are provided per pin, and the same start signal is provided from the outside for each of the start control circuits. Each of the start control circuits then determines the start timing for at least one timing generator accommodated therein by the variable set values, and starts to control each timing generator at the thus-determined start timing. Thus, timing signals which correspond to the respective variable set values are produced from the respective timing generators with high timing accuracy and in interlock with each other. It is possible to provide timing generators for a driver, for input/output (I/O) control, and for a comparator, and in this case it is easy to obtain the respective timing signals.

Abstract: An air bed conveying system conveys a workpiece while the workpiece is being floated by air under pressure which is ejected from a plurality of air ejection holes defined in air bed blocks that are supported on respective support blocks. Each of the support blocks is of an integral box-shaped configuration and made of a quartz material having a low thermal expansion coefficient. A plurality of vertical position adjusting mechanisms are disposed underneath each of the support blocks, for adjusting the support block in vertical position.

Abstract: An optical fiber element includes a non-armored optical glass fiber element having a numerical aperture of 0.35 or more, and a resin layer obtaining by applying a resin composition to a surface of the non-armored optical glass fiber element in contact therewith and by curing the resin composition, the cured resin layer essentially consisting of the resin composition having a Shore D hardness value of 65 or more defined in the Japanese Industrial Standards (JIS) at room temperature.

Abstract: An object of the present invention is to provide a time interval measurement circuit having especially high time measurement precision and resolution in time interval measurement between two signals and requiring short measurement time. In order to achieve the above described object, a time interval measurement circuit according to the present invention comprises two parallel transmission lines, differential output drivers connected to both ends of said transmission lines, a plurality of potential difference sensing means so disposed between said transmission lines at predetermined intervals as to generate an output signal upon an excess of potential difference between said two transmission lines over a predetermined level, and means for detecting, on the basis of output signals supplied from said potential difference sensing means, which potential difference sensing means has generated an output signal.

Abstract: A memory test apparatus for testing a high-performance memory having two or more memory functions, including a pattern generator for generating an algorithmic pattern to be inputted to a first memory block of a memory under test having at least two memory blocks, an auxiliary pattern generator for storing an output from the algorithmic pattern generator and for outputting an expected value to a second memory block of the memory under test at a preset timing based on the stored output, a comparator for comparing outputs from the first and second memory blocks with expected values for the memory blocks, and a memory for storing an output from the comparator.

Abstract: A variable-ratio frequency divider has a D flip-flop which makes possible high-speed operation, and the number of frequency divisions is made variable by changing the transmission delay time of a delay element included in a feedback loop from the output Q to a predetermined terminal of the D flip-flop.