Abstract: According to one embodiment, a semiconductor memory device includes a stacked structure including conductive layers arranged in a first direction, and a columnar structure extending in the first direction in the first stacked structure. The columnar structure includes a semiconductor layer extending in the first direction, a charge storage layer between the semiconductor layer and the stacked structure, a first insulating layer between the semiconductor layer and the charge storage layer, and a second insulating layer between the stacked structure and the charge storage layer. The charge storage layer is aluminum nitride with a wurtzite crystal structure in which the c-axis is oriented in a direction towards the first insulating layer from the second insulating layer.

Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.

Abstract: A storage device includes a first conductive layer and a second conductive layer, with an intermediate layer therebetween. The intermediate layer includes a first and second compound regions. The first compound region includes first and second adjacent portions and the second compound region includes third and fourth adjacent portions. Electrical resistance between the first and second conductive layers changes according to a polarity applied across the intermediate layer. In a first polarity state, a concentration of a first element in the first portion is higher than a concentration of the first element in the second portion of the first compound region. A thickness of the third portion in the first polarity state is greater than the thickness of the fourth portion in the first polarity state.

Abstract: A storage device includes a first conductive layer and a second conductive layer, with an intermediate layer therebetween. The intermediate layer includes a first and second compound regions. The first compound region includes first and second adjacent portions and the second compound region includes third and fourth adjacent portions. Electrical resistance between the first and second conductive layers changes according to a polarity applied across the intermediate layer. In a first polarity state, a concentration of a first element in the first portion is higher than a concentration of the first element in the second portion of the first compound region. A thickness of the third portion in the first polarity state is greater than the thickness of the fourth portion in the first polarity state.

Abstract: A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.

Abstract: A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.

Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.

Abstract: A battery case provided with a safety valve (4) in which a breakage groove (45) is used, wherein in order to stabilize the operation pressure, a lid (2) of the battery case has formed thereon: a thin plate portion (30) obtained by thinning a plate part (3); and a first recessed part (40) comprising a curved part (44) in which the thin plate portion (30) is indented inward, with respect to the case, in a curved shape. The breakage groove (45) for the safety valve (4) is formed at the bottom part (440) of the curved part (44). A first connecting portion (46) and a second connecting portion (47) of the plate part (3), which connect to the curved part (44) on both sides flanking the curved part (44), are at positions protruding toward the outside of the case from the plate part (3).

Abstract: The present invention provides an aluminum-alloy automotive underbody part having adequate strength even when using a part forged from an aluminum alloy casting material and an effective method for manufacturing said underbody part. The present invention pertains to an automotive underbody part characterized in being an aluminum alloy forged part in which the average inverse of the Schmid factor, calculated based on the crystal orientation in the direction of load stress in the maximum stress area when external force is applied, is 2.3 or more.

Abstract: A battery case provided with a safety valve (4) in which a breakage groove (45) is used, wherein in order to stabilize the operation pressure, a lid (2) of the battery case has formed thereon: a thin plate portion (30) obtained by thinning a plate part (3); and a first recessed part (40) comprising a curved part (44) in which the thin plate portion (30) is indented inward, with respect to the case, in a curved shape. The breakage groove (45) for the safety valve (4) is formed at the bottom part (440) of the curved part (44). A first connecting portion (46) and a second connecting portion (47) of the plate part (3), which connect to the curved part (44) on both sides flanking the curved part (44), are at positions protruding toward the outside of the case from the plate part (3).

Abstract: According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: According to one embodiment, a semiconductor device having a Ge— or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge.

Abstract: A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an Si1-xGex layer (0<x<0.5) on the (100) plane of the Ge nano wire.

Abstract: It is made possible to restrict strain relaxation even if a strained semiconductor element is formed on a very small minute layer. A semiconductor device includes: a substrate; a first semiconductor layer formed into a mesa shape above the substrate and having strain, and including source and drain regions of a first conductivity type located at a distance from each other, and a channel region of a second conductivity type different from the first conductivity type, the channel region being located between the source region and the drain region; second and third semiconductor layers formed on the source and drain regions, and controlling the strain of the first semiconductor layer, the second and third semiconductor layers containing impurities of the first conductivity type; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film.