Patents by Inventor Yoshihiko Shimanuki
Yoshihiko Shimanuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10515934Abstract: A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.Type: GrantFiled: May 28, 2018Date of Patent: December 24, 2019Assignee: Renesas Electronics CorporationInventor: Yoshihiko Shimanuki
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Patent number: 10090237Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.Type: GrantFiled: October 6, 2017Date of Patent: October 2, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshihiko Shimanuki
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Publication number: 20180277522Abstract: A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.Type: ApplicationFiled: May 28, 2018Publication date: September 27, 2018Inventor: Yoshihiko Shimanuki
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Patent number: 9991229Abstract: A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.Type: GrantFiled: August 6, 2015Date of Patent: June 5, 2018Assignee: Renesas Electronics CorporationInventor: Yoshihiko Shimanuki
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Publication number: 20180040552Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.Type: ApplicationFiled: October 6, 2017Publication date: February 8, 2018Inventor: Yoshihiko SHIMANUKI
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Patent number: 9831129Abstract: A semiconductor device manufacturing method which improves working efficiency. The method includes the step of transporting by air a package as a sealed moisture-proof bag which contains a case housing a semiconductor wafer laminate, in which the semiconductor wafer laminate has a plurality of semiconductor wafers stacked with a protective sheet interposed between semiconductor wafers. In order to facilitate separation of the protective sheet from the semiconductor wafers after unpacking the package, the protective sheet has a plurality of convex parts, a plurality of concave parts, and a flat part between a convex part and a concave part. A hole penetrating the protective sheet is made in each convex part and the center of the hole is located off the apex of the convex part.Type: GrantFiled: January 26, 2017Date of Patent: November 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshihiko Shimanuki
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Patent number: 9812388Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.Type: GrantFiled: November 22, 2016Date of Patent: November 7, 2017Assignee: Renesas Electronics CorporationInventor: Yoshihiko Shimanuki
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Publication number: 20170287783Abstract: A semiconductor device manufacturing method which improves working efficiency. The method includes the step of transporting by air a package as a sealed moisture-proof bag which contains a case housing a semiconductor wafer laminate, in which the semiconductor wafer laminate has a plurality of semiconductor wafers stacked with a protective sheet interposed between semiconductor wafers. In order to facilitate separation of the protective sheet from the semiconductor wafers after unpacking the package, the protective sheet has a plurality of convex parts, a plurality of concave parts, and a flat part between a convex part and a concave part. A hole penetrating the protective sheet is made in each convex part and the center of the hole is located off the apex of the convex part.Type: ApplicationFiled: January 26, 2017Publication date: October 5, 2017Inventor: Yoshihiko SHIMANUKI
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Publication number: 20170213788Abstract: A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.Type: ApplicationFiled: November 22, 2016Publication date: July 27, 2017Inventor: Yoshihiko SHIMANUKI
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Patent number: 9484288Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: GrantFiled: February 16, 2015Date of Patent: November 1, 2016Assignees: Renesas Technology Corporation, Renesas Semiconductor Package & Test Solutions Co., Ltd.Inventor: Yoshihiko Shimanuki
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Publication number: 20160276253Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventor: Yoshihiko Shimanuki
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Publication number: 20150348944Abstract: Wire connection failure in semiconductor device is prevented. A semiconductor device has a package substrate having, at the periphery of the main surface thereof, a plurality of bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the plurality of wires, and a plurality of solder bumps disposed on the back surface of the package substrate. The top of the loop of each of the wires is disposed outside the wire connecting portion so that the wire length wire can be increased in the connection between the bonding leads and the pads of the semiconductor chip. As a result, the wires have a stable loop shape and a wire connection failure can be prevented.Type: ApplicationFiled: August 6, 2015Publication date: December 3, 2015Inventor: Yoshihiko Shimanuki
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Publication number: 20150228558Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: ApplicationFiled: February 16, 2015Publication date: August 13, 2015Inventor: Yoshihiko Shimanuki
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Patent number: 8969138Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: GrantFiled: December 17, 2013Date of Patent: March 3, 2015Assignee: Renesas Electronics CorporationInventor: Yoshihiko Shimanuki
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Publication number: 20140106509Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicants: HITACHI YONEZAWA ELECTRONICS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventor: Yoshihiko Shimanuki
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Patent number: 8637965Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: GrantFiled: January 24, 2012Date of Patent: January 28, 2014Assignees: Renesas Electronics Corporation, Hitachi Yonezawa Electronics Co., LtdInventor: Yoshihiko Shimanuki
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Patent number: 8390133Abstract: There are constituted by a tab on which a semiconductor chip is mounted, a sealing portion formed by resin-sealing the semiconductor chip, a plurality of leads each having a mounted surface exposed to a peripheral portion of a rear surface of the sealing portion and a sealing-portion forming surface disposed on an opposite side thereto, and a wire for connecting a pad of the semiconductor chip and a lead, wherein the length between inner ends of the sealing-portion forming surfaces of the leads disposed so as to oppose to each other is formed to be larger than the length between inner ends of the mounted surfaces. Thereby, a chip mounting region surrounded by the inner end of the sealing-portion forming surface of each lead can be expanded and the size of the mountable chip is increased.Type: GrantFiled: June 27, 2012Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Yoshihiko Shimanuki, Yoshihiro Suzuki, Koji Tsuchiya
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Publication number: 20130001804Abstract: There are constituted by a tab on which a semiconductor chip is mounted, a sealing portion formed by resin-sealing the semiconductor chip, a plurality of leads each having a mounted surface exposed to a peripheral portion of a rear surface of the sealing portion and a sealing-portion forming surface disposed on an opposite side thereto, and a wire for connecting a pad of the semiconductor chip and a lead, wherein the length between inner ends of the sealing-portion forming surfaces of the leads disposed so as to oppose to each other is formed to be larger than the length between inner ends of the mounted surfaces. Thereby, a chip mounting region surrounded by the inner end of the sealing-portion forming surface of each lead can be expanded and the size of the mountable chip is increased.Type: ApplicationFiled: June 27, 2012Publication date: January 3, 2013Inventors: YOSHIHIKO SHIMANUKI, Yoshihiro Suzuki, Koji Tsuchiya
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Patent number: 8222720Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.Type: GrantFiled: November 24, 2010Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Yoshihiko Shimanuki, Yoshihiro Suzuki, Koji Tsuchiya
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Publication number: 20120146228Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: ApplicationFiled: January 24, 2012Publication date: June 14, 2012Applicants: HITACHI YONEZAWA ELECTRONICS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventor: Yoshihiko Shimanuki