Patents by Inventor Yoshihiko Shimanuki

Yoshihiko Shimanuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6943064
    Abstract: The semiconductor device includes tub 5 that is smaller than semiconductor chip 8, and which supports semiconductor chip 8; molded section 12 that is formed by resin-molding around semiconductor chip 8; suspension leads 4, including supporting portions 4a that support tub 5 and exposed portions 4b that are connected to supporting portions 4a and are exposed on back surface 12a of molded section 12, and are elevation processed in supporting portions 4a; leads 2 that are located around tub 5; and wires 10 that connect pads 7 of the semiconductor chip 8 with the corresponding leads 2; wherein the thickness of tub 5 and supporting portions 4a of suspension leads 4 is less than the thickness of exposed portions 4b, and back surface 8b of semiconductor chip 8 is firmly in contact with molding resin 11.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: September 13, 2005
    Assignees: Renesas Technology Corp., Hitachi Yonezawa Electronics Co., Ltd.
    Inventor: Yoshihiko Shimanuki
  • Patent number: 6930380
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: August 16, 2005
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Yoshihiko Shimanuki, Hisashi Hasunuma
  • Publication number: 20050176171
    Abstract: A method of manufacturing a thin, small-sized, inexpensive, non-leaded, resin-sealed type semiconductor device is disclosed. A flexible tape having plural terminals peelably through a first adhesive in a product forming portion formed on a main surface of the tape is provided, a semiconductor element is fixed to the main surface of the tape peelably through a second adhesive, electrodes formed on the semiconductor element and the terminals are connected together through conductive wires, an insulating resin layer is formed in an area including the semiconductor element and the wires on the main surface of the tape to cover the semiconductor element and the wires, and the tape on a back surface of the insulating resin layer is peeled, allowing the terminals to be exposed to the back surface of the insulating resin layer. Exposed surfaces of the terminals are each formed by a gold layer.
    Type: Application
    Filed: April 7, 2003
    Publication date: August 11, 2005
    Inventors: Yoshinori Miyaki, Yoshihiko Shimanuki, Hiromichi Suzuki, Fujio Ito
  • Patent number: 6927096
    Abstract: A method of producing a thin, non-lead type semiconductor device superior in packaging performance is to be provided. A recess and grooves are formed on a main surface of a conductive substrate in accordance with predetermined patterns to define plural compartments surrounded with the recess and grooves, and plural product-forming portions are formed each by one or plural recesses and plural compartments.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: August 9, 2005
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventor: Yoshihiko Shimanuki
  • Publication number: 20050003586
    Abstract: A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a conductive flat substrate (metal plate) of copper plate or the like, fixing semiconductor elements respectively to predetermined positions on the principal surface of the substrate by an insulating adhesive, electrically connecting electrodes on the surfaces of the semiconductor elements with predetermined partition parts of the substrate separate from the semiconductor elements by conductive wires, forming an insulating resin layer on the principal surface of the substrate to cover the semiconductor elements and wires, selectively removing the substrate from the rear of said substrate to form electrically independent partition parts whereof at least some are external electrode terminals, and selectively removing said resin layer to fragment the device into regions containing the semiconductor elements and the plural partition parts around the semiconductor elements.
    Type: Application
    Filed: August 2, 2004
    Publication date: January 6, 2005
    Inventors: Yoshihiko Shimanuki, Masayuki Suzuki
  • Publication number: 20040245622
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.
    Type: Application
    Filed: June 4, 2004
    Publication date: December 9, 2004
    Inventors: Yoshihiko Shimanuki, Hisashi Hasunuma
  • Publication number: 20040232442
    Abstract: The plurality of electrical leads of the semiconductor device have a connection portion exposed to the outer periphery on the back surface of the seal section and a thickness reduced portion formed to be thinner than said connection portion. The connection portion is provided with an inner groove and an outer groove in a wire bonding surface as disposed within the seal section of the connection portion. Wires are provided for electrical connection between the leads and pads of the semiconductor chip. The thickness reduced portion of the leads is covered by or coated with a sealing resin material while causing the wires to be contacted with the connection portion at specified part lying midway between the outer groove and inner groove to permit the thickness reduced portion of leads and the outer groove plus the inner groove to prevent the occurrence of any accidental lead drop-down detachment.
    Type: Application
    Filed: June 30, 2004
    Publication date: November 25, 2004
    Applicants: Hitachi, Ltd., Hitachi Yonezawa Electronics Co., Ltd.
    Inventor: Yoshihiko Shimanuki
  • Publication number: 20040140541
    Abstract: A semiconductor device is comprised of:
    Type: Application
    Filed: January 8, 2004
    Publication date: July 22, 2004
    Applicants: Renesas Technology Corporation, Hitachi Yonezawa Electronics Co., Ltd.
    Inventor: Yoshihiko Shimanuki
  • Publication number: 20040097017
    Abstract: A method of producing a thin, non-lead type semiconductor device superior in packaging performance is to be provided. A recess and grooves are formed on a main surface of a conductive substrate in accordance with predetermined patterns to define plural compartments surrounded with the recess and grooves, and plural product-forming portions are formed each by one or plural recesses and plural compartments.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 20, 2004
    Applicants: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventor: Yoshihiko Shimanuki
  • Patent number: 6700193
    Abstract: The semiconductor device includes tub 5 that is smaller than semiconductor chip 8, and which supports semiconductor chip 8; molded section 12 that is formed by resin-molding around semiconductor chip 8; suspension leads 4, including supporting portions 4a that support tub 5 and exposed portions 4b that are connected to supporting portions 4a and are exposed on back surface 12a of molded section 12, and are elevation processed in supporting portions 4a; leads 2 that are located around tub 5; and wires 10 that connect pads 7 of semiconductor chip 8 with the corresponding leads 2; wherein the thickness of tub 5 and supporting portions 4a of suspension leads 4 is less than the thickness of exposed portions 4b, and back surface 8b of semiconductor chip 8 is firmly in contact with molding resin 11.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: March 2, 2004
    Assignees: Renesas Technology Corporation, Hitachi Yonezawa Electronics Co., Ltd.
    Inventor: Yoshihiko Shimanuki
  • Publication number: 20030001249
    Abstract: A semiconductor device is disclosed which includes a tub (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tub suspension lead (4) for support of the tub (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outer
    Type: Application
    Filed: August 27, 2002
    Publication date: January 2, 2003
    Inventor: Yoshihiko Shimanuki
  • Publication number: 20020168796
    Abstract: A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a conductive flat substrate (metal plate) of copper plate or the like, fixing semiconductor elements respectively to predetermined positions on the principal surface of the substrate by an insulating adhesive, electrically connecting electrodes on the surfaces of the semiconductor elements with predetermined partition parts of the substrate separate from the semiconductor elements by conductive wires, forming an insulating resin layer on the principal surface of the substrate to cover the semiconductor elements and wires, selectively removing the substrate from the rear of said substrate to form electrically independent partition parts whereof at least some are external electrode terminals, and selectively removing said resin layer to fragment the device into regions containing the semiconductor elements and the plural partition parts around the semiconductor elements.
    Type: Application
    Filed: March 6, 2002
    Publication date: November 14, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yoshihiko Shimanuki, Masayuki Suzuki
  • Publication number: 20020079563
    Abstract: A semiconductor device is comprised of:
    Type: Application
    Filed: November 20, 2001
    Publication date: June 27, 2002
    Inventor: Yoshihiko Shimanuki