Patents by Inventor Yoshihiro AKUTSU
Yoshihiro AKUTSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220246631Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Applicant: KIOXIA CORPORATIONInventors: Yoshihiro AKUTSU, Ryota KATSUMATA
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Patent number: 11342348Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: GrantFiled: July 17, 2020Date of Patent: May 24, 2022Assignee: KIOXIA CORPORATIONInventors: Yoshihiro Akutsu, Ryota Katsumata
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Publication number: 20200350327Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: July 17, 2020Publication date: November 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yoshihiro AKUTSU, Ryota KATSUMATA
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Patent number: 10748916Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: GrantFiled: October 31, 2018Date of Patent: August 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoshihiro Akutsu, Ryota Katsumata
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Publication number: 20190074284Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: October 31, 2018Publication date: March 7, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yoshihiro AKUTSU, Ryota KATSUMATA
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Patent number: 10134751Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: GrantFiled: August 15, 2017Date of Patent: November 20, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoshihiro Akutsu, Ryota Katsumata
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Patent number: 9935121Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.Type: GrantFiled: March 8, 2016Date of Patent: April 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Konagai, Yoshihiro Akutsu, Masaru Kito
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Publication number: 20170373080Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: August 15, 2017Publication date: December 28, 2017Applicant: Toshiba Memory CorporationInventors: Yoshihiro AKUTSU, Ryota KATSUMATA
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Patent number: 9818753Abstract: In general, according to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first sub-conductive layer, a first insulating film. One portion of the first conductive layer overlaps at least one portion of the first sub-conductive layer in the first direction. One other portion of the first conductive layer overlaps at least one portion of the second conductive layer in the first direction. One portion of the first insulating film overlaps at least one portion of the second conductive layer in the second direction. The One portion of the first insulating film overlaps one portion of the first sub-conductive layer in the second direction. The second conductive layer overlap one other portion of the first insulating film in a direction intersecting the second direction.Type: GrantFiled: March 8, 2016Date of Patent: November 14, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshihiro Akutsu
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Patent number: 9768185Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: GrantFiled: May 11, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoshihiro Akutsu, Ryota Katsumata
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Patent number: 9741736Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and a first interconnect. When an imaginary first straight line extending in a second direction crossing a first direction is set, the plurality of columnar portions are divided into first sets of n (n is an integer number not less than 3 and not more than 32) columnar portions with center axes alternately disposed on both sides of the first straight line along the second direction and second sets of n columnar portions having position relationships of inversion of the first sets with respect to the first straight line, and the first sets and the second sets are alternately arranged.Type: GrantFiled: March 14, 2016Date of Patent: August 22, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihiro Akutsu
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Publication number: 20170110462Abstract: In general, according to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first sub-conductive layer, a first insulating film. One portion of the first conductive layer overlaps at least one portion of the first sub-conductive layer in the first direction. One other portion of the first conductive layer overlaps at least one portion of the second conductive layer in the first direction. One portion of the first insulating film overlaps at least one portion of the second conductive layer in the second direction. The One portion of the first insulating film overlaps one portion of the first sub-conductive layer in the second direction. The second conductive layer overlap one other portion of the first insulating film in a direction intersecting the second direction.Type: ApplicationFiled: March 8, 2016Publication date: April 20, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Yoshihiro AKUTSU
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Publication number: 20170077025Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and a first interconnect. When an imaginary first straight line extending in a second direction crossing a first direction is set, the plurality of columnar portions are divided into first sets of n (n is an integer number not less than 3 and not more than 32) columnar portions with center axes alternately disposed on both sides of the first straight line along the second direction and second sets of n columnar portions having position relationships of inversion of the first sets with respect to the first straight line, and the first sets and the second sets are alternately arranged.Type: ApplicationFiled: March 14, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Yoshihiro AKUTSU
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Publication number: 20170077131Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.Type: ApplicationFiled: March 8, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi KONAGAI, Yoshihiro Akutsu, Masaru Kito
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Publication number: 20170069657Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar, and memory film. The substrate has a major surface. The stacked body is provided on the major surface. The stacked body includes a plurality of conductive layers arranged in a first direction and separated from each other. The first direction is orthogonal to the major surface. The pillar includes a first portion and a second portion. The first portion extends along the first direction in the stacked body. The second portion is provided in the substrate. The first portion includes a region overlapping one of the conductive layers in a second direction orthogonal to the first direction. The memory film is provided between the stacked body and the pillar. A first length of the region along the second direction is less than a second length of the second portion along the second direction.Type: ApplicationFiled: February 22, 2016Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hironobu HAMANAKA, Yoshihiro Akutsu
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Publication number: 20160254271Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro AKUTSU, Ryota Katsumata
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Patent number: 9362298Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: GrantFiled: March 12, 2015Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro Akutsu, Ryota Katsumata
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Publication number: 20160079250Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: March 12, 2015Publication date: March 17, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro AKUTSU, Ryota Katsumata
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Publication number: 20160079265Abstract: This nonvolatile semiconductor memory device includes a semiconductor substrate and a first semiconductor layer formed on a surface of the semiconductor substrate. A memory cell array is formed by coupling a plurality of memory cells in series, and includes a memory string formed to extend in a first direction vertical to the surface of the semiconductor substrate. A contact extends in a direction vertical to the semiconductor substrate, and has one end coupled to the first semiconductor layer. The contact includes: a second semiconductor layer that is formed in the first semiconductor layer and has a higher impurity concentration than that of the first semiconductor layer; a silicide film that has one end coupled to the second semiconductor layer and extends in the first direction; and a metal film formed on an inner wall of the silicide film.Type: ApplicationFiled: March 12, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yoshihiro AKUTSU, Hisataka Meguro
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Publication number: 20160079255Abstract: According to one embodiment, a stacked body includes electrode layers and first insulating layers alternately stacked. An isolation region extends in the stacked body, the isolation region dividing the stacked body into first regions. First semiconductor members extend in one of the first regions in a stacked direction of the stacked body. A memory film is provided between one of the first semiconductor members and one of the electrode layers. A insulating region extends in the one of the first regions in the stacked direction. A composition of a second region of the one of the electrode layers is different from a composition of a third region of the one of the electrode layers. The second region is in contact with the insulating region, the third region being in contact with the isolation region.Type: ApplicationFiled: August 5, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi SONEHARA, Masaru KITO, Takashi SHIMIZU, Yoshihiro AKUTSU