Patents by Inventor Yoshihiro AKUTSU

Yoshihiro AKUTSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9159613
    Abstract: According to an embodiment, a method for fabricating a pattern includes forming a mask covering a first layer, and a second layer selectively provided on the first layer, and forming a groove dividing the first layer and the second layer using the mask. The mask includes a first portion formed on a region of the first layer on a first side of the second layer, a second portion formed on a region of the first layer on a second side of the second layer opposite to the first side, first extending parts extending over the second layer from the first portion toward the second portion, and second extending parts extending over the second layer from the second portion toward the first portion. Each of the second extending parts is located between the first extending parts adjacent to each other.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Akutsu, Masaru Kidoh, Tsuneo Uenaka, Tadashi Iguchi
  • Patent number: 9136358
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second channel body layer penetrating the selection gate electrode and the interlayer insulating film and connected to the first channel body; a gate insulating film provided between the selection gate electrode and the second channel body layer; a second insulating layer provided on the gate insulating film and on the selection gate electrode; a contact layer provided on the second insulating layer; and a diffusion layer provided between the contact layer and the second insulating layer and connected to the second channel body layer and the contact layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Akutsu, Hiroshi Shinohara, Ryota Katsumata
  • Publication number: 20150061068
    Abstract: According to an embodiment, a method for fabricating a pattern includes forming a mask covering a first layer, and a second layer selectively provided on the first layer, and forming a groove dividing the first layer and the second layer using the mask. The mask includes a first portion formed on a region of the first layer on a first side of the second layer, a second portion formed on a region of the first layer on a second side of the second layer opposite to the first side, first extending parts extending over the second layer from the first portion toward the second portion, and second extending parts extending over the second layer from the second portion toward the first portion. Each of the second extending parts is located between the first extending parts adjacent to each other.
    Type: Application
    Filed: March 11, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Akutsu, Masaru Kidoh, Tsuneo Uenaka, Tadashi Iguchi
  • Publication number: 20140284692
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second channel body layer penetrating the selection gate electrode and the interlayer insulating film and connected to the first channel body; a gate insulating film provided between the selection gate electrode and the second channel body layer; a second insulating layer provided on the gate insulating film and on the selection gate electrode; a contact layer provided on the second insulating layer; and a diffusion layer provided between the contact layer and the second insulating layer and connected to the second channel body layer and the contact layer.
    Type: Application
    Filed: September 6, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro AKUTSU, Hiroshi SHINOHARA, Ryota KATSUMATA
  • Patent number: 8669608
    Abstract: According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru Sato, Megumi Ishiduki, Masaru Kidoh, Atsushi Konno, Yoshihiro Akutsu, Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata
  • Publication number: 20130075805
    Abstract: According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.
    Type: Application
    Filed: March 14, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru SATO, Megumi ISHIDUKI, Masaru KIDOH, Atsushi KONNO, Yoshihiro AKUTSU, Masaru KITO, Yoshiaki FUKUZUMI, Ryota KATSUMATA