Patents by Inventor Yoshihiro Asai
Yoshihiro Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004242Abstract: A liquid crystal display panel includes: an array substrate; a counter substrate; a liquid crystal layer located between the array substrate and the counter substrate; and an alignment film formed on a surface facing the liquid crystal layer in each of the array substrate and the counter substrate. In a plan view, the liquid crystal display panel includes a display region, a non-display region adjacent to the display region, and a light-transmitting region located in the non-display region. At least one of the array substrate or the counter substrate includes a wall portion surrounding the light-transmitting region in the non-display region of the surface facing the liquid crystal layer, and the alignment film is not formed in a range surrounded by the wall portion.Type: ApplicationFiled: May 30, 2023Publication date: January 4, 2024Inventors: Yoshihiro ASAI, Isao Ogasawara
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Patent number: 11552109Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.Type: GrantFiled: January 19, 2021Date of Patent: January 10, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihiro Asai, Satoshi Horiuchi, Seiya Kawamorita, Shinji Matsubara, Seijirou Gyouten
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Patent number: 11526062Abstract: A display device includes a display substrate, a plurality of source drive circuit elements, gate drive circuits, and a plurality of gate connection lines. The plurality of gate connection lines pass through inter-element regions between the source drive circuit elements in plan view, and pass through mounting regions. Gate terminals connected to the gate connection lines are formed at positions facing the inter-element regions in a direction from the inter-element regions toward an FPC (Y2 direction).Type: GrantFiled: April 4, 2022Date of Patent: December 13, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihiro Asai, Isao Ogasawara
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Publication number: 20220326561Abstract: A display device includes a display substrate, a plurality of source drive circuit elements, gate drive circuits, and a plurality of gate connection lines. The plurality of gate connection lines pass through inter-element regions between the source drive circuit elements in plan view, and pass through mounting regions. Gate terminals connected to the gate connection lines are formed at positions facing the inter-element regions in a direction from the inter-element regions toward an FPC (Y2 direction).Type: ApplicationFiled: April 4, 2022Publication date: October 13, 2022Inventors: Yoshihiro ASAI, Isao OGASAWARA
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Patent number: 11374037Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).Type: GrantFiled: February 14, 2018Date of Patent: June 28, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Satoshi Horiuchi, Yoshihiro Asai, Isao Ogasawara, Masakatsu Tominaga, Yoshihito Hara
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Publication number: 20220119638Abstract: A method for improving the comparative tracking index of a thermoplastic resin, as measured in compliance with IEC60112, 3rd edition, is disclosed by blending a carbodiimide compound in the thermoplastic resin; use of a carbodiimide compound for improving the comparative tracking index of a thermoplastic resin, as measured in compliance with IEC60112, 3rd edition; and a tracking resistance improving agent for a thermoplastic resin, for improving the comparative tracking index of the thermoplastic resin, as measured in compliance with IEC60112, 3rd edition. The carbodiimide compound is preferably used at a ratio of 0.01 parts by mass or more with respect to 100 parts by mass of the thermoplastic resin.Type: ApplicationFiled: March 24, 2020Publication date: April 21, 2022Applicant: Polyplastics Co., Ltd.Inventors: Itsuki Saito, Yoshihiro Asai, Kazuya Goshima
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Patent number: 11150706Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.Type: GrantFiled: May 28, 2020Date of Patent: October 19, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Satoshi Horiuchi, Seijirou Gyouten, Yoshihiro Asai, Seiya Kawamorita
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Publication number: 20210225879Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.Type: ApplicationFiled: January 19, 2021Publication date: July 22, 2021Inventors: Yoshihiro ASAI, Satoshi HORIUCHI, Seiya KAWAMORITA, Shinji MATSUBARA, Seijirou GYOUTEN
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Publication number: 20200379523Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.Type: ApplicationFiled: May 28, 2020Publication date: December 3, 2020Inventors: Satoshi HORIUCHI, Seijirou GYOUTEN, Yoshihiro ASAI, Seiya KAWAMORITA
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Patent number: 10795225Abstract: Provided is a display device in which connection defects in terminal parts can be suppressed, and a method for producing the same. An active matrix substrate 1 of a display device includes gate lines, data lines arranged so as to intersect with the gate lines, pixel electrodes, counter electrodes forming capacitors between the same and the pixel electrodes, and signal lines that are connected with the counter electrodes and supply a driving signal for touch detection. Further, the active matrix substrate 1 includes a display driving circuit that supplies a control signal to at least either the gate lines or the data lines, and a touch detection driving circuit that supplies a driving signal for touch detection. Still further, the active matrix substrate 1 includes a plurality of terminal parts Ta to which the display driving circuit and the touch detection driving circuit are connected, and the terminal parts Ta have a common layer structure.Type: GrantFiled: June 7, 2017Date of Patent: October 6, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Masaki Maeda, Masakatsu Tominaga, Isao Ogasawara, Kuniko Maeno, Shingo Kamitani, Yasuhiro Mimura, Satoshi Horiuchi, Yoshihiro Asai
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Patent number: 10775660Abstract: Provided is a touch-panel-equipped display device that can improve the touch sensing accuracy, without decreases in the display quality, and a method for producing the same. A touch-panel-equipped display device includes an active matrix substrate 1. The active matrix substrate 1 includes a plurality of pixel electrodes 31; a plurality of counter electrodes 21 forming capacitors between the same and the pixel electrodes 31; a plurality of touch detection lines 22; a first insulating layer 461; and a second insulating layer 462. The touch detection lines 22 are connected with any of the counter electrodes 21, and supply a driving signal for touch detection to the counter electrodes 21 connected therewith. Between each pixel electrode 31 and the corresponding one of the counter electrodes 21, the second insulating layer 462 is arranged.Type: GrantFiled: June 7, 2017Date of Patent: September 15, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Masaki Maeda, Masakatsu Tominaga, Isao Ogasawara, Kuniko Maeno, Shingo Kamitani, Yasuhiro Mimura, Satoshi Horiuchi, Yoshihiro Asai
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Patent number: 10777156Abstract: A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.Type: GrantFiled: August 30, 2018Date of Patent: September 15, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Satoshi Horiuchi, Seijirou Gyouten, Sachio Tsujino, Isao Ogasawara, Yoshihiro Asai
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Publication number: 20200249510Abstract: An array substrate includes an insulating substrate, a source metal film disposed in a layer upper than the insulating substrate, a first insulating film disposed on the source metal film, and an alignment film disposed on the first insulating film. The first insulating film includes a groove portion including a through portion and a recess portion. The through portion extends through the first insulating film and the recess portion is recessed in the first insulating film so as not to extend through the first insulating film. The through portion does not overlap the source metal film and the recess portion overlaps at least the source metal film.Type: ApplicationFiled: January 29, 2020Publication date: August 6, 2020Inventors: YOSHIHIRO ASAI, SATOSHI HORIUCHI, SEIJIROU GYOUTEN
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Publication number: 20200043958Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).Type: ApplicationFiled: February 14, 2018Publication date: February 6, 2020Inventors: Satoshi HORIUCHI, Yoshihiro ASAI, Isao OGASAWARA, Masakatsu TOMINAGA, Yoshihito HARA
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Publication number: 20190265531Abstract: Provided is a touch-panel-equipped display device that can improve the touch sensing accuracy, without decreases in the display quality, and a method for producing the same. A touch-panel-equipped display device includes an active matrix substrate 1. The active matrix substrate 1 includes a plurality of pixel electrodes 31; a plurality of counter electrodes 21 forming capacitors between the same and the pixel electrodes 31; a plurality of touch detection lines 22; a first insulating layer 461; and a second insulating layer 462. The touch detection lines 22 are connected with any of the counter electrodes 21, and supply a driving signal for touch detection to the counter electrodes 21 connected therewith. Between each pixel electrode 31 and the corresponding one of the counter electrodes 21, the second insulating layer 462 is arranged.Type: ApplicationFiled: June 7, 2017Publication date: August 29, 2019Applicant: SHARP KABUSHIKI KAISHAInventors: YOSHIHITO HARA, MASAKI MAEDA, MASAKATSU TOMINAGA, ISAO OGASAWARA, KUNIKO MAENO, SHINGO KAMITANI, YASUHIRO MIMURA, SATOSHI HORIUCHI, YOSHIHIRO ASAI
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Publication number: 20190258105Abstract: Provided is a display device in which connection defects in terminal parts can be suppressed, and a method for producing the same. An active matrix substrate 1 of a display device includes gate lines, data lines arranged so as to intersect with the gate lines, pixel electrodes, counter electrodes forming capacitors between the same and the pixel electrodes, and signal lines that are connected with the counter electrodes and supply a driving signal for touch detection. Further, the active matrix substrate 1 includes a display driving circuit that supplies a control signal to at least either the gate lines or the data lines, and a touch detection driving circuit that supplies a driving signal for touch detection. Still further, the active matrix substrate 1 includes a plurality of terminal parts Ta to which the display driving circuit and the touch detection driving circuit are connected, and the terminal parts Ta have a common layer structure.Type: ApplicationFiled: June 7, 2017Publication date: August 22, 2019Inventors: YOSHIHITO HARA, MASAKI MAEDA, MASAKATSU TOMINAGA, ISAO OGASAWARA, KUNIKO MAENO, SHINGO KAMITANI, YASUHIRO MIMURA, SATOSHI HORIUCHI, YOSHIHIRO ASAI
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Publication number: 20190073973Abstract: A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.Type: ApplicationFiled: August 30, 2018Publication date: March 7, 2019Inventors: SATOSHI HORIUCHI, SEIJIROU GYOUTEN, SACHIO TSUJINO, ISAO OGASAWARA, YOSHIHIRO ASAI
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Patent number: 9443781Abstract: In a liquid crystal display device (1) according to one aspect of the present invention, each of a first gate driver (17) supplying a gate signal to a first gate line (10) of a first display part (8) and a second gate driver (18) supplying a gate signal to a second gate line (13) of a second display part (9) are constituted to comprise a transistor formed on one surface of an array substrate (2).Type: GrantFiled: January 24, 2014Date of Patent: September 13, 2016Assignee: Sharp Kabushiki KaishaInventors: Yoshihiro Asai, Katsuhiro Okada, Isao Ogasawara, Masahiro Yoshida
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Publication number: 20150364396Abstract: In a liquid crystal display device (1) according to one aspect of the present invention, each of a first gate driver (17) supplying a gate signal to a first gate line (10) of a first display part (8) and a second gate driver (18) supplying a gate signal to a second gate line (13) of a second display part (9) are constituted to comprise a transistor formed on one surface of an array substrate (2).Type: ApplicationFiled: January 24, 2014Publication date: December 17, 2015Inventors: Yoshihiro ASAI, Katsuhiro OKADA, Isao OGASAWARA, Masahiro YOSHIDA
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Publication number: 20150077317Abstract: A matrix substrate includes: a pixel region (A); a first line (G) that is connected to the pixels arrayed in one direction in the pixel region (A); a second line (S) that is connected to the pixels arrayed in a direction different from the one direction; a terminal region (17a) in which a terminal for inputting a signal is arranged; and a left lead line (kS3, kS4) that goes around the left side of the pixel region (A) from a side of the pixel region (A) where the terminal region (17a) is provided and is led out to the opposite side, and a right lead line (kS1, kS2) that goes around the right side and is led out to the opposite side. The left lead line and the right lead line are connected to the first line (G) or the second line (S) via a collective region (D).Type: ApplicationFiled: April 18, 2013Publication date: March 19, 2015Inventors: Masakazu Miyamoto, Toshiaki Fujihara, Kazuhiro Yoshikawa, Yoshihiro Asai