Patents by Inventor Yoshihiro Asai

Yoshihiro Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240004242
    Abstract: A liquid crystal display panel includes: an array substrate; a counter substrate; a liquid crystal layer located between the array substrate and the counter substrate; and an alignment film formed on a surface facing the liquid crystal layer in each of the array substrate and the counter substrate. In a plan view, the liquid crystal display panel includes a display region, a non-display region adjacent to the display region, and a light-transmitting region located in the non-display region. At least one of the array substrate or the counter substrate includes a wall portion surrounding the light-transmitting region in the non-display region of the surface facing the liquid crystal layer, and the alignment film is not formed in a range surrounded by the wall portion.
    Type: Application
    Filed: May 30, 2023
    Publication date: January 4, 2024
    Inventors: Yoshihiro ASAI, Isao Ogasawara
  • Patent number: 11552109
    Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: January 10, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiro Asai, Satoshi Horiuchi, Seiya Kawamorita, Shinji Matsubara, Seijirou Gyouten
  • Patent number: 11526062
    Abstract: A display device includes a display substrate, a plurality of source drive circuit elements, gate drive circuits, and a plurality of gate connection lines. The plurality of gate connection lines pass through inter-element regions between the source drive circuit elements in plan view, and pass through mounting regions. Gate terminals connected to the gate connection lines are formed at positions facing the inter-element regions in a direction from the inter-element regions toward an FPC (Y2 direction).
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: December 13, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiro Asai, Isao Ogasawara
  • Publication number: 20220326561
    Abstract: A display device includes a display substrate, a plurality of source drive circuit elements, gate drive circuits, and a plurality of gate connection lines. The plurality of gate connection lines pass through inter-element regions between the source drive circuit elements in plan view, and pass through mounting regions. Gate terminals connected to the gate connection lines are formed at positions facing the inter-element regions in a direction from the inter-element regions toward an FPC (Y2 direction).
    Type: Application
    Filed: April 4, 2022
    Publication date: October 13, 2022
    Inventors: Yoshihiro ASAI, Isao OGASAWARA
  • Patent number: 11374037
    Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 28, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Satoshi Horiuchi, Yoshihiro Asai, Isao Ogasawara, Masakatsu Tominaga, Yoshihito Hara
  • Publication number: 20220119638
    Abstract: A method for improving the comparative tracking index of a thermoplastic resin, as measured in compliance with IEC60112, 3rd edition, is disclosed by blending a carbodiimide compound in the thermoplastic resin; use of a carbodiimide compound for improving the comparative tracking index of a thermoplastic resin, as measured in compliance with IEC60112, 3rd edition; and a tracking resistance improving agent for a thermoplastic resin, for improving the comparative tracking index of the thermoplastic resin, as measured in compliance with IEC60112, 3rd edition. The carbodiimide compound is preferably used at a ratio of 0.01 parts by mass or more with respect to 100 parts by mass of the thermoplastic resin.
    Type: Application
    Filed: March 24, 2020
    Publication date: April 21, 2022
    Applicant: Polyplastics Co., Ltd.
    Inventors: Itsuki Saito, Yoshihiro Asai, Kazuya Goshima
  • Patent number: 11150706
    Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 19, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Satoshi Horiuchi, Seijirou Gyouten, Yoshihiro Asai, Seiya Kawamorita
  • Publication number: 20210225879
    Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 22, 2021
    Inventors: Yoshihiro ASAI, Satoshi HORIUCHI, Seiya KAWAMORITA, Shinji MATSUBARA, Seijirou GYOUTEN
  • Publication number: 20200379523
    Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Inventors: Satoshi HORIUCHI, Seijirou GYOUTEN, Yoshihiro ASAI, Seiya KAWAMORITA
  • Patent number: 10795225
    Abstract: Provided is a display device in which connection defects in terminal parts can be suppressed, and a method for producing the same. An active matrix substrate 1 of a display device includes gate lines, data lines arranged so as to intersect with the gate lines, pixel electrodes, counter electrodes forming capacitors between the same and the pixel electrodes, and signal lines that are connected with the counter electrodes and supply a driving signal for touch detection. Further, the active matrix substrate 1 includes a display driving circuit that supplies a control signal to at least either the gate lines or the data lines, and a touch detection driving circuit that supplies a driving signal for touch detection. Still further, the active matrix substrate 1 includes a plurality of terminal parts Ta to which the display driving circuit and the touch detection driving circuit are connected, and the terminal parts Ta have a common layer structure.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: October 6, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Masaki Maeda, Masakatsu Tominaga, Isao Ogasawara, Kuniko Maeno, Shingo Kamitani, Yasuhiro Mimura, Satoshi Horiuchi, Yoshihiro Asai
  • Patent number: 10775660
    Abstract: Provided is a touch-panel-equipped display device that can improve the touch sensing accuracy, without decreases in the display quality, and a method for producing the same. A touch-panel-equipped display device includes an active matrix substrate 1. The active matrix substrate 1 includes a plurality of pixel electrodes 31; a plurality of counter electrodes 21 forming capacitors between the same and the pixel electrodes 31; a plurality of touch detection lines 22; a first insulating layer 461; and a second insulating layer 462. The touch detection lines 22 are connected with any of the counter electrodes 21, and supply a driving signal for touch detection to the counter electrodes 21 connected therewith. Between each pixel electrode 31 and the corresponding one of the counter electrodes 21, the second insulating layer 462 is arranged.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: September 15, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Masaki Maeda, Masakatsu Tominaga, Isao Ogasawara, Kuniko Maeno, Shingo Kamitani, Yasuhiro Mimura, Satoshi Horiuchi, Yoshihiro Asai
  • Patent number: 10777156
    Abstract: A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 15, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Satoshi Horiuchi, Seijirou Gyouten, Sachio Tsujino, Isao Ogasawara, Yoshihiro Asai
  • Publication number: 20200249510
    Abstract: An array substrate includes an insulating substrate, a source metal film disposed in a layer upper than the insulating substrate, a first insulating film disposed on the source metal film, and an alignment film disposed on the first insulating film. The first insulating film includes a groove portion including a through portion and a recess portion. The through portion extends through the first insulating film and the recess portion is recessed in the first insulating film so as not to extend through the first insulating film. The through portion does not overlap the source metal film and the recess portion overlaps at least the source metal film.
    Type: Application
    Filed: January 29, 2020
    Publication date: August 6, 2020
    Inventors: YOSHIHIRO ASAI, SATOSHI HORIUCHI, SEIJIROU GYOUTEN
  • Publication number: 20200043958
    Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).
    Type: Application
    Filed: February 14, 2018
    Publication date: February 6, 2020
    Inventors: Satoshi HORIUCHI, Yoshihiro ASAI, Isao OGASAWARA, Masakatsu TOMINAGA, Yoshihito HARA
  • Publication number: 20190265531
    Abstract: Provided is a touch-panel-equipped display device that can improve the touch sensing accuracy, without decreases in the display quality, and a method for producing the same. A touch-panel-equipped display device includes an active matrix substrate 1. The active matrix substrate 1 includes a plurality of pixel electrodes 31; a plurality of counter electrodes 21 forming capacitors between the same and the pixel electrodes 31; a plurality of touch detection lines 22; a first insulating layer 461; and a second insulating layer 462. The touch detection lines 22 are connected with any of the counter electrodes 21, and supply a driving signal for touch detection to the counter electrodes 21 connected therewith. Between each pixel electrode 31 and the corresponding one of the counter electrodes 21, the second insulating layer 462 is arranged.
    Type: Application
    Filed: June 7, 2017
    Publication date: August 29, 2019
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: YOSHIHITO HARA, MASAKI MAEDA, MASAKATSU TOMINAGA, ISAO OGASAWARA, KUNIKO MAENO, SHINGO KAMITANI, YASUHIRO MIMURA, SATOSHI HORIUCHI, YOSHIHIRO ASAI
  • Publication number: 20190258105
    Abstract: Provided is a display device in which connection defects in terminal parts can be suppressed, and a method for producing the same. An active matrix substrate 1 of a display device includes gate lines, data lines arranged so as to intersect with the gate lines, pixel electrodes, counter electrodes forming capacitors between the same and the pixel electrodes, and signal lines that are connected with the counter electrodes and supply a driving signal for touch detection. Further, the active matrix substrate 1 includes a display driving circuit that supplies a control signal to at least either the gate lines or the data lines, and a touch detection driving circuit that supplies a driving signal for touch detection. Still further, the active matrix substrate 1 includes a plurality of terminal parts Ta to which the display driving circuit and the touch detection driving circuit are connected, and the terminal parts Ta have a common layer structure.
    Type: Application
    Filed: June 7, 2017
    Publication date: August 22, 2019
    Inventors: YOSHIHITO HARA, MASAKI MAEDA, MASAKATSU TOMINAGA, ISAO OGASAWARA, KUNIKO MAENO, SHINGO KAMITANI, YASUHIRO MIMURA, SATOSHI HORIUCHI, YOSHIHIRO ASAI
  • Publication number: 20190073973
    Abstract: A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 7, 2019
    Inventors: SATOSHI HORIUCHI, SEIJIROU GYOUTEN, SACHIO TSUJINO, ISAO OGASAWARA, YOSHIHIRO ASAI
  • Patent number: 9443781
    Abstract: In a liquid crystal display device (1) according to one aspect of the present invention, each of a first gate driver (17) supplying a gate signal to a first gate line (10) of a first display part (8) and a second gate driver (18) supplying a gate signal to a second gate line (13) of a second display part (9) are constituted to comprise a transistor formed on one surface of an array substrate (2).
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 13, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Asai, Katsuhiro Okada, Isao Ogasawara, Masahiro Yoshida
  • Publication number: 20150364396
    Abstract: In a liquid crystal display device (1) according to one aspect of the present invention, each of a first gate driver (17) supplying a gate signal to a first gate line (10) of a first display part (8) and a second gate driver (18) supplying a gate signal to a second gate line (13) of a second display part (9) are constituted to comprise a transistor formed on one surface of an array substrate (2).
    Type: Application
    Filed: January 24, 2014
    Publication date: December 17, 2015
    Inventors: Yoshihiro ASAI, Katsuhiro OKADA, Isao OGASAWARA, Masahiro YOSHIDA
  • Publication number: 20150077317
    Abstract: A matrix substrate includes: a pixel region (A); a first line (G) that is connected to the pixels arrayed in one direction in the pixel region (A); a second line (S) that is connected to the pixels arrayed in a direction different from the one direction; a terminal region (17a) in which a terminal for inputting a signal is arranged; and a left lead line (kS3, kS4) that goes around the left side of the pixel region (A) from a side of the pixel region (A) where the terminal region (17a) is provided and is led out to the opposite side, and a right lead line (kS1, kS2) that goes around the right side and is led out to the opposite side. The left lead line and the right lead line are connected to the first line (G) or the second line (S) via a collective region (D).
    Type: Application
    Filed: April 18, 2013
    Publication date: March 19, 2015
    Inventors: Masakazu Miyamoto, Toshiaki Fujihara, Kazuhiro Yoshikawa, Yoshihiro Asai