Patents by Inventor Yoshihiro Asai

Yoshihiro Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8941185
    Abstract: An active matrix substrate of the present invention includes: a first signal line and a second signal line which are aligned in a column direction in which the first signal line and the second signal line extend; a first transistor and a second transistor; and a first electrode and a second electrode, the first signal line being connected via the first transistor to the first electrode, and the second signal line being connected via the second transistor to the second electrode, and the first signal line having a first end which is one of both ends of the first signal line and faces the second signal line, the first end including a tapered part which is tapered toward the second signal line. This makes it possible to prevent a leakage defect from occurring between two signal lines which are aligned in a direction in which the two signal lines extend.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: January 27, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Asai, Satoshi Horiuchi, Kazuyori Mitsumoto
  • Publication number: 20130335684
    Abstract: A functional panel (FP) includes a COM substrate (4) and an SEG substrate (3) that face each other. The functional panel (FP) is combined with a display panel (LP) via an adhesive. The COM substrate (4), which is provided farther from the display panel (LP) than the SEG substrate (3) is, has edges (E1, E2) that face each other. The SEG substrate (3), which is provided closer to the display panel (LP) than the COM substrate (4) is, has (i) an edge (E3) provided along and inside the edge (E1) when viewed from above and (ii) an edge (E4) provided along and inside the edge (E2) when viewed from above. This effectively prevents the occurrence of a defective external shape.
    Type: Application
    Filed: January 18, 2012
    Publication date: December 19, 2013
    Inventors: Kazuhiro Yoshikawa, Kazunori Tanimoto, Masayuki Tsuji, Takayuki Hayano, Nobuhiro Nakata, Yoshihiro Asai, Masahiro Yoshida, Tatsuji Saitoh, Isao Ogasawara
  • Publication number: 20130307085
    Abstract: An active matrix substrate of the present invention includes: a first signal line and a second signal line which are aligned in a column direction in which the first signal line and the second signal line extend; a first transistor and a second transistor; and a first electrode and a second electrode, the first signal line being connected via the first transistor to the first electrode, and the second signal line being connected via the second transistor to the second electrode, and the first signal line having a first end which is one of both ends of the first signal line and faces the second signal line, the first end including a tapered part which is tapered toward the second signal line. This makes it possible to prevent a leakage defect from occurring between two signal lines which are aligned in a direction in which the two signal lines extend.
    Type: Application
    Filed: February 2, 2012
    Publication date: November 21, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiro Asai, Satoshi Horiuchi, Kazuyori Mitsumoto
  • Patent number: 6793793
    Abstract: A novel method of electrochemical treatment such as electroplating, etc. and an electrochemical reaction apparatus thereof which is high in reactability and able to be electrochemically reacted efficiently, which is small or zero in amount of generation of liquid waste such as electrolytic solution and cleaning liquid and therefore, amicable to the environment, and in which it is no more required to clean the electrode, etc. with cleaning liquid after reaction. Electrochemical reaction is executed in a reaction vessel (6) containing matter (5) which is in a supercritical or subcritical state and an electrolytic solution (1), and after reaction, the supercritical or subcritical matter (5) is shifted into a state of the matter (5) before being shifted into a critical state.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: September 21, 2004
    Inventors: Hideo Yoshida, Seizo Miyata, Yoshihiro Asai, Masato Sone, Fumiko Iwao, Hiroe Asai
  • Publication number: 20030019756
    Abstract: A novel method of electrochemical treatment such as electroplating, etc. and an electrochemical reaction apparatus thereof which is high in reactability and able to be electrochemically reacted efficiently, which is small or zero in amount of generation of liquid waste such as electrolytic solution and cleaning liquid and therefore, amicable to the environment, and in which it is no more required to clean the electrode, etc. with cleaning liquid after reaction. Electrochemical reaction is executed in a reaction vessel (6) containing matter (5) which is in a supercritical or subcritical state and an electrolytic solution (1), and after reaction, the supercritical or subcritical matter (5) is shifted into a state of the matter (5) before being shifted into a critical state.
    Type: Application
    Filed: March 4, 2002
    Publication date: January 30, 2003
    Inventors: Hideo Yoshida, Seizo Miyata, Yoshihiro Asai, Masato Sone, Fumiko Iwao, Hiroe Asai
  • Patent number: 6445372
    Abstract: A flat-panel display device includes a display control unit having a scanning line driver for periodically selecting at least two adjacent scanning lines and driving such lines together. A scanning controller controls a driver to turn on elements connected to a first one of the adjacent scanning lines located on one side of a row of the pixels capacitively coupled thereto and driven for the row of pixels, and elements connected to a second one of the adjacent scanning lines located on another side of the row of pixels capacitively coupled thereto and not driven for the row of pixels, at a substantially identical timing, and to turn off the elements connected to second adjacent scanning line earlier than the elements connected to the first adjacent scanning line.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: September 3, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Asai
  • Patent number: 6262541
    Abstract: Each signal-input pad in signal-line pad groups and scanning-line pad groups has enough width and length for contacting with inspection probe and serves as an inspection pad. Hence, the space for disposing inspection pads separately from the connection pads are no more needed, thereby reducing width of periphery connection area in the array substrate.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: July 17, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Asai
  • Patent number: 6166713
    Abstract: An active matrix display device including an array substrate that has a signal lines and scanning lines that cross each other, switching elements, and pixel electrodes that are provided in the vicinity of the respective crossing points. The pixel electrodes are connected to the lines via respective switching elements. A scanning signal supply provides a scanning signal that has a first voltage that turns on the switching elements and a second voltage that turns off the switching elements. A first connector electrically connects the scanning lines to each other. A driving circuit having nonlinear resistor elements sets the voltage of the first connector to be substantially equal to the second voltage.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Asai, Hiroyuki Kimura
  • Patent number: 5835171
    Abstract: The present invention relates to the structure of an active matrix type liquid crystal display device in which a channel length of a thin film transistor without increasing resistance of a scanning line region to improve a switching characteristic. A slit is formed at the channel of the thin film transistor formed on the scanning line region. The slit is used as a mask and a pattern of a channel protection film for determining the channel of the thin film transistor is formed by exposure form a back surface of a substrate. According to this method, a desirable channel length can be obtained, and the scanning line region, facing to the channel through the slit, functions as an auxiliary region, so that the resistance of the scanning line region can be reduced.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: November 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Hanazawa, Tomoko Kitazawa, Yoshihiro Asai, Katsuhiko Inada, Tetsuya Iizuka
  • Patent number: 5708483
    Abstract: In an active matrix type display device using TFTs as switching elements, in order to remarkably improve the aperture ratio and, at the same time, largely lower a dissipation power, an extending electrode is provided as one unit to a scanning line and light is shut off at those areas between a signal line and two display pixel electrodes situated adjacent the signal line, the two display pixel electrodes being arranged with the signal line interposed.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: January 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Asai
  • Patent number: 5610736
    Abstract: An active matrix type display device including a plurality of thin film transistors disposed at crossing points of a plurality of scanning lines and a plurality of signal lines, and serving as switching elements for controlling pixels of the display device. Each pixel has a elongated electrode extending in overlapped relation with signal line. A dielectric layer, composed of the same layer as a gate insulating layer and a semiconductor layer, which is the same layer as the active layer of a thin film transistor, is interposed between the signal line and the elongated electrode, and a part of the elongated electrode serves as a electrode of a storage capacitor which is electrically coupled with the pixel.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: March 11, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Asai