Patents by Inventor Yoshihiro Hirota

Yoshihiro Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10748782
    Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate, which includes: embedding a polymer having a urea bond in a recess formed in the substrate by supplying a material for polymerization from above a sacrificial film to the substrate and forming a polymer film made of the polymer having the urea bond, wherein a surface of the substrate is covered with the sacrificial film, the recess including an opening of the sacrificial film that is formed by a patterning; removing the polymer film formed on the sacrificial film while leaving the polymer embedded in the recess; removing the sacrificial film in a state in which the polymer is embedded in the recess; and subsequently, removing the polymer embedded in the recess.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 18, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tatsuya Yamaguchi, Reiji Niino, Makoto Fujikawa, Yoshihiro Hirota, Rong Yang, Tomonari Yamamoto
  • Publication number: 20190394384
    Abstract: A video display apparatus includes: a tone mapping processor that converts, by using dynamic metadata indicating a maximum luminance of a video in each of a plurality of time intervals included in a predetermined period, a luminance of the video in each time interval based on conversion characteristics according to the maximum luminance of the video in the time interval; and a display. The tone mapping processor switches between: a first operation of performing the tone mapping process by using first dynamic metadata that indicates the maximum luminance that is constant over the plurality of time intervals, the first dynamic metadata being generated by using static metadata that indicates a maximum luminance of the video in the predetermined period; and a second operation of performing the tone mapping process by using second dynamic metadata in which the maximum luminance varies over the plurality of time intervals.
    Type: Application
    Filed: February 26, 2018
    Publication date: December 26, 2019
    Inventors: Masaya YAMAMOTO, Masayuki KOZUKA, Yoshiichiro KASHIWAGI, Toshiroh NISHIO, Kazuhiko KOUNO, Hiroshi YAHATA, Takeshi HIROTA, Yoshihiro MORI
  • Publication number: 20190387134
    Abstract: A video display apparatus includes: a tone mapping processor that performs a tone mapping process of converting a luminance of a video by using conversion characteristics according to a maximum luminance of the video; and a display that displays the video that has undergone the tone mapping process. The tone mapping processor switches between a first tone mapping process of dynamically changing the conversion characteristics according to a time-depend change in the maximum luminance of the video and a second tone mapping process that is performed using constant conversion characteristics irrespective of the time-depend change in the maximum luminance of the video. When the tone mapping process used is switched from the second tone mapping process to the first tone mapping process, the conversion characteristics used is changed gradually or stepwise from the constant conversion characteristics to dynamically changing conversion characteristics over a plurality of frames.
    Type: Application
    Filed: February 26, 2018
    Publication date: December 19, 2019
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki KOZUKA, Masaya YAMAMOTO, Yoshiichiro KASHIWAGI, Toshiroh NISHIO, Kazuhiko KOUNO, Hiroshi YAHATA, Takeshi HIROTA, Yoshihiro MORI
  • Publication number: 20190259355
    Abstract: A video processing system includes: an acquirer that acquires video data including a main video; a format acquirer that acquires a display format that indicates a luminance dynamic range format displayable by a video display apparatus; a generator that generates first characteristics information that indicates first dynamic luminance characteristics that correspond to the display format by using the video data when a luminance dynamic range format of the main video indicated by the video data is different from the display format, the first dynamic luminance characteristics being dynamic luminance characteristics indicating a time-dependent change in luminance characteristics of the main video; and a video transmitter that outputs the first characteristics information generated by the generator.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 22, 2019
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki KOZUKA, Masaya YAMAMOTO, Toshiroh NISHIO, Kazuhiko KOUNO, Yoshiichiro KASHIWAGI, Takeshi HIROTA, Hiroshi YAHATA, Yoshihiro MORI
  • Publication number: 20190251680
    Abstract: A video display apparatus includes: a video receiver that acquires video data including a main video; a generator that generates first characteristics information that indicates first dynamic luminance characteristics by using the video data when a luminance dynamic range format of the main video indicated by the video data is different from a display format that indicates a luminance dynamic range format displayable by the video display apparatus, the first dynamic luminance characteristics being dynamic luminance characteristics indicating a time-dependent change in luminance characteristics of the main video and correspond to the display format; a tone mapping processor that performs a tone mapping process of converting a luminance of the main video based on conversion characteristics according to the first dynamic luminance characteristics indicated by the first characteristics information generated by the generator; and a display that displays the main video that has undergone the tone mapping process.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 15, 2019
    Inventors: Masayuki KOZUKA, Masaya YAMAMOTO, Toshiroh NISHIO, Kazuhiko KOUNO, Yoshiichiro KASHIWAGI, Takeshi HIROTA, Hiroshi YAHATA, Yoshihiro MORI
  • Publication number: 20190222721
    Abstract: A video display system includes: a tone mapping processor that performs a tone mapping process of converting a luminance of a video by using conversion characteristics according to a maximum luminance of the video; and a display that displays the video that has undergone the tone mapping process. The tone mapping processor switches between a first tone mapping process of dynamically changing the conversion characteristics according to a time-dependent change in the maximum luminance of the video and a second tone mapping process that is performed using constant conversion characteristics irrespective of the time-dependent change in the maximum luminance of the video.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 18, 2019
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaya YAMAMOTO, Masayuki KOZUKA, Yoshiichiro KASHIWAGI, Toshiroh NISHIO, Kazuhiko KOUNO, Hiroshi YAHATA, Takeshi HIROTA, Yoshihiro MORI
  • Publication number: 20190222818
    Abstract: A video display apparatus includes: a tone mapping processor that performs a tone mapping process of converting a luminance of a video by using conversion characteristics according to a maximum luminance of the video; and a display that displays the video that has undergone the tone mapping process. The tone mapping processor switches between a first tone mapping process of dynamically changing the conversion characteristics according to a time-dependent change in the maximum luminance of the video and a second tone mapping process that is performed using constant conversion characteristics irrespective of the time-dependent change in the maximum luminance of the video.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 18, 2019
    Inventors: Masaya YAMAMOTO, Masayuki KOZUKA, Yoshiichiro KASHIWAGI, Toshiroh NISHIO, Kazuhiko KOUNO, Hiroshi YAHATA, Takeshi HIROTA, Yoshihiro MORI
  • Publication number: 20190122894
    Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate, which includes: embedding a polymer having a urea bond in a recess formed in the substrate by supplying a material for polymerization from above a sacrificial film to the substrate and forming a polymer film made of the polymer having the urea bond, wherein a surface of the substrate is covered with the sacrificial film, the recess including an opening of the sacrificial film that is formed by a patterning; removing the polymer film formed on the sacrificial film while leaving the polymer embedded in the recess; removing the sacrificial film in a state in which the polymer is embedded in the recess; and subsequently, removing the polymer embedded in the recess.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 25, 2019
    Inventors: Tatsuya YAMAGUCHI, Reiji NIINO, Makoto FUJIKAWA, Yoshihiro HIROTA, Rong YANG, Tomonari YAMAMOTO
  • Publication number: 20170287727
    Abstract: A metal hard mask for etching an etching target film that is present on a target object to be processed is formed of an amorphous alloy film that is formed by a thin film formation technique. It is preferable to use a physical vapor deposition method as the thin film formation technique, and sputtering is suitable for the use among physical vapor deposition methods. This metal hard mask is obtained by forming an amorphous alloy film on the etching target film by a thin film formation technique and patterning the amorphous alloy film.
    Type: Application
    Filed: July 10, 2015
    Publication date: October 5, 2017
    Inventors: Yuuki KIKUCHI, Hiroyuki NAGAI, Yoshihiro HIROTA, Mikio SUZUKI
  • Publication number: 20140162428
    Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.
    Type: Application
    Filed: February 11, 2014
    Publication date: June 12, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hajime NAKABAYASHI, Kenichi OYAMA, Yoshihiro HIROTA
  • Patent number: 8687405
    Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 1, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hajime Nakabayashi, Kenichi Oyama, Yoshihiro Hirota
  • Publication number: 20140034893
    Abstract: A switch device used in a crossbar memory array having a non-volatile memory includes: a laminated body formed of a semiconductor film and an insulating film laminated on the semiconductor film; and a pair of electrode layers having the laminated body therebetween. The semiconductor film is made of a semiconductor material having an I-V characteristic with a negative resistance region.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 6, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hajime NAKABAYASHI, Yoshihiro HIROTA
  • Publication number: 20140038430
    Abstract: In a method for processing an object by heating the object, microwaves are irradiated to the object. In the microwave irradiation, the object is forcedly cooled.
    Type: Application
    Filed: July 18, 2013
    Publication date: February 6, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yoshiro Kabe, Taichi Monden, Kouji Shimomura, Kentaro Shiraga, Yoshimasa Watanabe, Yoshihiro Hirota, Junichi Kitagawa
  • Publication number: 20120314493
    Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 13, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hajime NAKABAYASHI, Kenichi OYAMA, Yoshihiro HIROTA
  • Patent number: 8318614
    Abstract: A Plasma processing apparatus (100) introduces microwaves into a chamber (1) by a plane antenna (31) which has a plurality of holes. A material gas, which contains a nitrogen-containing compound and a silicon-containing compound, is introduced into the chamber (1) by using the plasma processing apparatus, and plasma is generated by the microwaves. Then, a silicon nitride film is deposited by the plasma on a surface of an object to be processed. The trap density of the silicon nitride film is controlled by adjusting the conditions of the plasma CVD process.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: November 27, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi, Yoshihiro Hirota
  • Patent number: 8258571
    Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: September 4, 2012
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Tetsuo Endoh, Masayuki Kohno, Tatsuo Nishita, Minoru Honda, Toshio Nakanishi, Yoshihiro Hirota
  • Patent number: 8247289
    Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: August 21, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
  • Patent number: 8241982
    Abstract: A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: August 14, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Yoshihiro Hirota, Yoshihiro Sato, Nobuo Okumura
  • Publication number: 20120184107
    Abstract: In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O(1D2) radicals produced using a processing gas that contains oxygen are dominant.
    Type: Application
    Filed: September 29, 2010
    Publication date: July 19, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Sato, Toshihiko Shiozawa, Tatsuo Nishita, Yoshihiro Hirota
  • Patent number: 8076892
    Abstract: A stator position adjustment method for a motor drive device that includes a motor case, a rotor shaft supported by the motor case in order to rotate a rotor inside the motor case, and a stator disposed at an outer circumference of the rotor concentrically with the rotor and having a configuration in which the stator is tightened and secured to the motor case by a tightening unit that tightens the stator along a rotor axis. The method includes the steps of setting a first tolerance range as a maximum tolerance range of a stator axis in which a first gap is formed between an outer circumference surface of the stator and an inner circumference surface of the motor case; measuring a position of the stator axis; and adjusting the position of the stator axis within the first tolerance range based on a measured position of the stator axis.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: December 13, 2011
    Assignees: Aisin AW Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Yasunori Oguri, Tomotaka Murakami, Yoshihiro Hirota, Akira Isogai, Takehito Jinno, Akira Takasaki, Tatsuhiko Mizutani, Hiroyuki Hattori