Patents by Inventor Yoshihiro Hirota
Yoshihiro Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953510Abstract: A management system including at least one processor, wherein the processor is configured to acquire an image obtained by imaging a sample container containing a sample, recognize relevant information related to reliability of a test result related to the sample based on the image, and derive reliability information indicating the reliability of the test result related to the sample based on the recognized relevant information.Type: GrantFiled: July 12, 2021Date of Patent: April 9, 2024Assignee: FUJIFILM CORPORATIONInventors: Takeya Meguro, Kazuhiro Hirota, Yoshihiro Seto, Kaku Irisawa, Hirotaka Watano, Taiji Iwasaki, Tatsuyuki Denawa, Haruyasu Nakatsugawa
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Patent number: 10748782Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate, which includes: embedding a polymer having a urea bond in a recess formed in the substrate by supplying a material for polymerization from above a sacrificial film to the substrate and forming a polymer film made of the polymer having the urea bond, wherein a surface of the substrate is covered with the sacrificial film, the recess including an opening of the sacrificial film that is formed by a patterning; removing the polymer film formed on the sacrificial film while leaving the polymer embedded in the recess; removing the sacrificial film in a state in which the polymer is embedded in the recess; and subsequently, removing the polymer embedded in the recess.Type: GrantFiled: October 19, 2018Date of Patent: August 18, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Tatsuya Yamaguchi, Reiji Niino, Makoto Fujikawa, Yoshihiro Hirota, Rong Yang, Tomonari Yamamoto
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Publication number: 20190122894Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate, which includes: embedding a polymer having a urea bond in a recess formed in the substrate by supplying a material for polymerization from above a sacrificial film to the substrate and forming a polymer film made of the polymer having the urea bond, wherein a surface of the substrate is covered with the sacrificial film, the recess including an opening of the sacrificial film that is formed by a patterning; removing the polymer film formed on the sacrificial film while leaving the polymer embedded in the recess; removing the sacrificial film in a state in which the polymer is embedded in the recess; and subsequently, removing the polymer embedded in the recess.Type: ApplicationFiled: October 19, 2018Publication date: April 25, 2019Inventors: Tatsuya YAMAGUCHI, Reiji NIINO, Makoto FUJIKAWA, Yoshihiro HIROTA, Rong YANG, Tomonari YAMAMOTO
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Publication number: 20170287727Abstract: A metal hard mask for etching an etching target film that is present on a target object to be processed is formed of an amorphous alloy film that is formed by a thin film formation technique. It is preferable to use a physical vapor deposition method as the thin film formation technique, and sputtering is suitable for the use among physical vapor deposition methods. This metal hard mask is obtained by forming an amorphous alloy film on the etching target film by a thin film formation technique and patterning the amorphous alloy film.Type: ApplicationFiled: July 10, 2015Publication date: October 5, 2017Inventors: Yuuki KIKUCHI, Hiroyuki NAGAI, Yoshihiro HIROTA, Mikio SUZUKI
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Publication number: 20140162428Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.Type: ApplicationFiled: February 11, 2014Publication date: June 12, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Hajime NAKABAYASHI, Kenichi OYAMA, Yoshihiro HIROTA
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Patent number: 8687405Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.Type: GrantFiled: June 4, 2012Date of Patent: April 1, 2014Assignee: Tokyo Electron LimitedInventors: Hajime Nakabayashi, Kenichi Oyama, Yoshihiro Hirota
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Publication number: 20140038430Abstract: In a method for processing an object by heating the object, microwaves are irradiated to the object. In the microwave irradiation, the object is forcedly cooled.Type: ApplicationFiled: July 18, 2013Publication date: February 6, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Yoshiro Kabe, Taichi Monden, Kouji Shimomura, Kentaro Shiraga, Yoshimasa Watanabe, Yoshihiro Hirota, Junichi Kitagawa
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Publication number: 20140034893Abstract: A switch device used in a crossbar memory array having a non-volatile memory includes: a laminated body formed of a semiconductor film and an insulating film laminated on the semiconductor film; and a pair of electrode layers having the laminated body therebetween. The semiconductor film is made of a semiconductor material having an I-V characteristic with a negative resistance region.Type: ApplicationFiled: August 2, 2013Publication date: February 6, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Hajime NAKABAYASHI, Yoshihiro HIROTA
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Publication number: 20120314493Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.Type: ApplicationFiled: June 4, 2012Publication date: December 13, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Hajime NAKABAYASHI, Kenichi OYAMA, Yoshihiro HIROTA
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Patent number: 8318614Abstract: A Plasma processing apparatus (100) introduces microwaves into a chamber (1) by a plane antenna (31) which has a plurality of holes. A material gas, which contains a nitrogen-containing compound and a silicon-containing compound, is introduced into the chamber (1) by using the plasma processing apparatus, and plasma is generated by the microwaves. Then, a silicon nitride film is deposited by the plasma on a surface of an object to be processed. The trap density of the silicon nitride film is controlled by adjusting the conditions of the plasma CVD process.Type: GrantFiled: March 25, 2008Date of Patent: November 27, 2012Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi, Yoshihiro Hirota
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Patent number: 8258571Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.Type: GrantFiled: June 20, 2008Date of Patent: September 4, 2012Assignees: Tokyo Electron Limited, Tohoku UniversityInventors: Tetsuo Endoh, Masayuki Kohno, Tatsuo Nishita, Minoru Honda, Toshio Nakanishi, Yoshihiro Hirota
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Patent number: 8247289Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.Type: GrantFiled: August 23, 2006Date of Patent: August 21, 2012Assignee: Ibiden Co., Ltd.Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
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Patent number: 8241982Abstract: A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film.Type: GrantFiled: November 9, 2010Date of Patent: August 14, 2012Assignee: Tokyo Electron LimitedInventors: Yoshihiro Hirota, Yoshihiro Sato, Nobuo Okumura
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Publication number: 20120184107Abstract: In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O(1D2) radicals produced using a processing gas that contains oxygen are dominant.Type: ApplicationFiled: September 29, 2010Publication date: July 19, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Yoshihiro Sato, Toshihiko Shiozawa, Tatsuo Nishita, Yoshihiro Hirota
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Patent number: 8076892Abstract: A stator position adjustment method for a motor drive device that includes a motor case, a rotor shaft supported by the motor case in order to rotate a rotor inside the motor case, and a stator disposed at an outer circumference of the rotor concentrically with the rotor and having a configuration in which the stator is tightened and secured to the motor case by a tightening unit that tightens the stator along a rotor axis. The method includes the steps of setting a first tolerance range as a maximum tolerance range of a stator axis in which a first gap is formed between an outer circumference surface of the stator and an inner circumference surface of the motor case; measuring a position of the stator axis; and adjusting the position of the stator axis within the first tolerance range based on a measured position of the stator axis.Type: GrantFiled: April 3, 2008Date of Patent: December 13, 2011Assignees: Aisin AW Co., Ltd., Toyota Jidosha Kabushiki KaishaInventors: Yasunori Oguri, Tomotaka Murakami, Yoshihiro Hirota, Akira Isogai, Takehito Jinno, Akira Takasaki, Tatsuhiko Mizutani, Hiroyuki Hattori
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Publication number: 20110073931Abstract: A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film.Type: ApplicationFiled: November 9, 2010Publication date: March 31, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Yoshihiro HIROTA, Yoshihiro SATO, Nobuo OKUMURA
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Publication number: 20110053381Abstract: Disclosed is a method for modifying an insulating film with plasma using a plasma processing apparatus which introduces a microwave into a processing chamber through a plane antenna having a plurality of holes. Processing gas containing a noble gas and oxygen is introduced into the processing chamber and microwave is introduced into the processing chamber through the plane antenna. Plasma composed mainly of O2+ ions and O(1D2) radicals is generated in a pressure condition within a range of 6.7 Pa to 267 Pa to modify the insulating film with the plasma.Type: ApplicationFiled: August 4, 2010Publication date: March 3, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Takashi KOBAYASHI, Daisuke KATAYAMA, Yoshihiro SATO, Junji HORII, Yoshihiro HIROTA
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Patent number: 7897498Abstract: The present invention is a method of manufacturing a semiconductor device from a layered body including: a semiconductor substrate; a high dielectric film formed on the semiconductor substrate; and an SiC-based film formed on a position upper than the high dielectric film, the SiC-based film having an anti-reflective function and a hardmask function. The present invention comprises a plasma-processing step for plasma-processing the SiC-based film and the high dielectric film to modify the SiC-based film and the high dielectric film by an action of a plasma; and a cleaning step for wet-cleaning the SiC-based film and the high dielectric film modified in the plasma-processing step to collectively remove the SiC-based film and the high dielectric film.Type: GrantFiled: November 29, 2005Date of Patent: March 1, 2011Assignee: Tokyo Electron LimitedInventors: Glenn Gale, Yoshihiro Hirota, Yusuke Muraki, Genji Nakamura, Masato Kushibiki, Naoki Shindo, Akitaka Shimizu, Shigeo Ashigaki, Yoshihiro Kato
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Publication number: 20100283097Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.Type: ApplicationFiled: June 20, 2008Publication date: November 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Tetsuo Endoh, Masayuki Kohno, Tatsuo Nishita, Minoru Honda, Toshio Nakanishi, Yoshihiro Hirota
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Publication number: 20100176441Abstract: In a nonvolatile semiconductor memory device of the method which enables a single cell to store more than or equal to 2-bit information, it is possible to prevent wire failure and ensure high operation reliability. The nonvolatile semiconductor memory device 200 includes a trench 203 having a round wall portion 203b; a tunnel oxide film 205, silicon nitride films 207a and 207b as charge trapping regions, a silicon dioxide film 209, a gate electrode 211, and a first source/drain region 213a and a second source/drain region 213b formed on Si substrates 201 arranged to have the gate electrode 211 therebetween.Type: ApplicationFiled: June 6, 2008Publication date: July 15, 2010Applicant: TOKYO ELECTRON LIMITEDInventor: Yoshihiro Hirota