Patents by Inventor Yoshihiro Kusuyama

Yoshihiro Kusuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6900462
    Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: May 31, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
  • Publication number: 20050092996
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Application
    Filed: November 2, 2004
    Publication date: May 5, 2005
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Publication number: 20040164296
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 &mgr;m or more.
    Type: Application
    Filed: November 24, 2003
    Publication date: August 26, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporation
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Publication number: 20040140471
    Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
    Type: Application
    Filed: October 10, 2003
    Publication date: July 22, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
  • Publication number: 20040084699
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japan corporation
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Patent number: 6686228
    Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: February 3, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
  • Patent number: 6657260
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 &mgr;m or more.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: December 2, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Patent number: 6642089
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: November 4, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20030054653
    Abstract: The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.
    Type: Application
    Filed: March 19, 2002
    Publication date: March 20, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20020197846
    Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
    Type: Application
    Filed: July 3, 2002
    Publication date: December 26, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
  • Publication number: 20020171085
    Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.
    Type: Application
    Filed: March 4, 2002
    Publication date: November 21, 2002
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama, Shunpei Yamazaki
  • Publication number: 20020163049
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Application
    Filed: March 26, 2002
    Publication date: November 7, 2002
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Patent number: 6475836
    Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: November 5, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
  • Publication number: 20020158288
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 &mgr;m or more.
    Type: Application
    Filed: February 21, 2002
    Publication date: October 31, 2002
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Patent number: 6372523
    Abstract: An etching method and a device therefor are provided to detect the etching end point with high accuracy and reproducibility. In an etching method and device, in dry etching, a variation of a self-bias voltage as a time elapses is measured, and a time where a differentiation value becomes 0 when the variation of the self-bias voltage is differentiated is regarded as an end point.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: April 16, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Tomohiko Sato, Yoshihiro Kusuyama, Koji Ono