Patents by Inventor Yoshihiro Morimoto

Yoshihiro Morimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090203160
    Abstract: A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate comprising a driving circuit region and a pixel region. First and second active layers are disposed on the substrate in the driving circuit region and in the pixel region, respectively. The first active layer has a grain size greater than that of the second active layer. Two gate structures are disposed on the first and second active layers, respectively, in which each gate structure comprises a stack of a gate dielectric layer and a gate layer. A reflector is disposed on the substrate under the first active layer and insulated from the first active layer. A method for fabricating a system for displaying images including the TFT device is also disclosed.
    Type: Application
    Filed: April 21, 2009
    Publication date: August 13, 2009
    Applicant: TPO Displays Corp.
    Inventors: Yoshihiro Morimoto, Ryan Lee, Hanson Liu, Feng-Yi Chen
  • Publication number: 20090015817
    Abstract: An exposure apparatus configured to expose a substrate to light to transfer a pattern of a reticle onto the substrate includes a reticle stage configured to mount the reticle, a structure configured to support the reticle stage, a plurality of first supporting members configured to support the structure; and a second supporting member configured to support the structure outside an area formed by connecting the three first supporting members. The second supporting member includes a unit configured to dampen vibration of the structure.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 15, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshihiro Morimoto
  • Patent number: 7439114
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Publication number: 20080128704
    Abstract: An image display system has a multi-gate thin film transistor (TFT) disposed on a transparent substrate. The multi-gate TFT includes a silicon film layer, a first electrode and a reflecting layer. The silicon film layer is formed on the transparent substrate and has a first crystallization zone and a second crystallization zone, which are not adjacent to each other. A grain size of the first crystallization zone is smaller than a grain size of the second crystallization zone. The first electrode corresponding to the first crystallization zone is disposed on the silicon film layer. The reflecting layer corresponding to the second crystallization zone is disposed on the transparent substrate. The silicon film layer is disposed on the transparent substrate and the reflecting layer.
    Type: Application
    Filed: November 9, 2007
    Publication date: June 5, 2008
    Inventors: Yoshihiro Morimoto, Ryan Lee, Hanson Liu, Fengyi Chen
  • Publication number: 20080042131
    Abstract: A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate comprising a driving circuit region and a pixel region. First and second active layers are disposed on the substrate in the driving circuit region and in the pixel region, respectively. The first active layer has a grain size greater than that of the second active layer. Two gate structures are disposed on the first and second active layers, respectively, in which each gate structure comprises a stack of a gate dielectric layer and a gate layer. A reflector is disposed on the substrate under the first active layer and insulated from the first active layer. A method for fabricating a system for displaying images including the TFT device is also disclosed.
    Type: Application
    Filed: August 15, 2006
    Publication date: February 21, 2008
    Inventors: Yoshihiro Morimoto, Ryan Lee, Hanson Liu, Feng-Yi Chen
  • Publication number: 20080035995
    Abstract: A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate having a pixel region. An active layer is disposed on the substrate of the pixel region, comprising a channel region, a pair of source/drain regions separated by the channel region. The channel region comprises dopants with a first conductivity type and a second conductivity type opposite to the first conductivity type. A gate structure is disposed on the active layer, comprising a stack of a gate dielectric layer and a gate layer. A method for fabricating a system for displaying images including the TFT device is also disclosed.
    Type: Application
    Filed: August 11, 2006
    Publication date: February 14, 2008
    Inventors: Yoshihiro Morimoto, Ryan Lee, Hanson Liu, Feng-Yi Chen
  • Publication number: 20080017937
    Abstract: A system for displaying images comprises a thin film transistor (TFT) device comprising first and second active layers disposed on a substrate in the driving circuit region and in the pixel region, respectively. Each active layer comprises a channel region, a source/drain region and a lightly doped region formed therebetween. Two gate structures are disposed on the first and second active layers, respectively. Each gate structure comprises a stacked first and second gate dielectric layers and a gate layer, and the second gate dielectric layer has a length shorter than that of the first gate dielectric layer but longer than the gate length of the gate layer. The lightly doped region of the first active layer has a length different from that of the second active layer.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 24, 2008
    Inventors: Yoshihiro Morimoto, Ryan Lee
  • Publication number: 20070285592
    Abstract: A method for fabricating a system for displaying images is provided, wherein the system comprises a low temperature polysilicon thin film transistor (LTPS-TFT) substrate. The method comprises providing a substrate comprising a first metal layer and a silicon film layer. The silicon film layer is illuminated t by a laser light having a wavelength larger than 400 nm. The silicon film layer is heated to crystallize by absorbing a part of the laser light, and is heated to re-crystallize by absorbing another part of the laser light, which passes through the silicon film layer and is reflected from the first metal layer to the silicon film layer.
    Type: Application
    Filed: April 16, 2007
    Publication date: December 13, 2007
    Inventors: Yoshihiro Morimoto, Ryan Lee, Hanson Liu
  • Publication number: 20070076145
    Abstract: A liquid crystal display panel having a plurality of pixels is provided. Each pixel may include a first substrate, a second substrate, a liquid crystal layer, a reflective layer and a cover layer. A surface of the second substrate includes a second transparent electrode. The liquid crystal layer is disposed between the first substrate and the second substrate. The reflective layer is disposed over at least a portion of the second transparent electrode. The cover layer is disposed over the reflective layer.
    Type: Application
    Filed: October 4, 2005
    Publication date: April 5, 2007
    Inventors: Yoshihiro Morimoto, An Shih, Yi-Wen Tai
  • Patent number: 7163850
    Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: January 16, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuhiko Oda, Toshifumi Yamaji, Shiro Nakanishi, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 7084052
    Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: August 1, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kiichi Hirano, Naoya Sotani, Toshifumi Yamaji, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 7061017
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: June 13, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Patent number: 7045818
    Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: May 16, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yushi Jinno, Shiro Nakanishi, Kyoko Hirai, Tsutomu Yamada, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Publication number: 20050287825
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Application
    Filed: August 18, 2005
    Publication date: December 29, 2005
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi kuwahara
  • Publication number: 20050227090
    Abstract: A anti-reflection film with pen scratch resistance has a low refractive index layer formed from a raw material composition containing silicon oxide and a crosslinking agent as main components. The raw material composition contains 1 to 10 wt % of a polymerization initiator and 1 to 5 wt % of a polysiloxane resin with respect to the sum of silicon oxide and the crosslinking agent.
    Type: Application
    Filed: July 4, 2003
    Publication date: October 13, 2005
    Applicant: NOF CORPORATION
    Inventors: Kensuke Yoshioka, Yoshihiro Morimoto
  • Patent number: 6875675
    Abstract: An a-Si film formed on an insulating substrate is irradiated with a laser to obtain a p-Si film, which is then exposed to an oxidation atmosphere to form a surface oxide film. The surface oxide film is then removed to reduce the height of a projection generated on the surface of the p-Si film, thereby planarizing the surface of the p-Si film.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: April 5, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Yoshihiro Morimoto
  • Publication number: 20050042809
    Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 24, 2005
    Inventors: Nobuhiko Oda, Toshifumi Yamaji, Shiro Nakanishi, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 6858512
    Abstract: An a-Si film (12) formed on an insulating substrate (10) is irradiated with a laser so that the a-Si film (12) is fused and recrystallized to form a p-Si film (13). Projections (100) generated on the p-Si film (13) at this stage are eliminated by irradiation of ion beams at the incident angle of 60° to 90° using an ion milling method to planarize the surface of the p-Si film (13), thereby creating sufficient insulation between the p-Si film (13) and gate electrodes (15).
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: February 22, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshihiro Morimoto, Kiyoshi Yoneda
  • Publication number: 20050035348
    Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.
    Type: Application
    Filed: September 20, 2004
    Publication date: February 17, 2005
    Inventors: Nobuhiko Oda, Toshifumi Yamaji, Shiro Nakanishi, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Publication number: 20050014316
    Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.
    Type: Application
    Filed: August 13, 2004
    Publication date: January 20, 2005
    Inventors: Kiichi Hirano, Naoya Sotani, Toshifumi Yamaji, Yoshihiro Morimoto, Kiyoshi Yoneda