Abstract: Provided is a semiconductor device including: a p-type silicon substrate; a p-well which is formed in the silicon substrate, and which has a planar shape with no hole; an n-well integrally formed, in the silicon substrate, in a planar shape obtained by inverting the pattern of the p-well; a first and a second gate electrodes formed respectively on the two wells; an n-type source/drain region formed in the p-well beside the first gate electrode; a p-type impurity diffusion region for well contact which is formed in the p-well, and to which a first substrate bias voltage is applied; a p-type source/drain region formed in the n-well beside the second gate electrode; and an n-type impurity diffusion region for well contact which is formed in the n-well, and to which a second substrate bias voltage is applied.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the <100> direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is formed on a silicon substrate so as to cover the device isolation structure.

Abstract: The semiconductor device comprises logic blocks 12 forming a logic circuit, and interconnection regions 14. A gate interconnection 32a including the gate electrode of a load transistor L1 and the gate electrode of a driver transistor D1, and the source/drain diffused layer 38 of a load transistor L2 are connected to each other by a conductor plug 50b. A gate interconnection 32b including the gate electrode of a load transistor L2 and the gate electrode of a driver transistor D2, and the source/drain diffused layer 35 of the load transistor L1 are connected to each other by a conductor plug 50c. The source/drain diffused layer 37 of a transfer transistor T1 and the source/drain diffused layer 37 of the first driver transistor D1 are made common, and the source/drain diffused layer 40 of the transfer transistor T2 and the source/drain diffused layer 40 of the driver transistor D2 are made common. Accordingly, the area for the memory cells to be formed in can be made very small.

Abstract: The semiconductor device comprises an interconnection buried in an interconnection groove formed in a lower insulating film, and an upper insulating film having a contact hole formed down to an end part of the interconnection. The interconnection groove is formed by using a design pattern having a main interconnection portion 100 and an extended portion 104 provided at an end part of a main interconnection portion 100 for forming the interconnection and extended perpendicularly to an extending direction of the main interconnection portion 100.

Abstract: A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.

Abstract: The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n, sandwiching the channel region; and a pocket region 40 formed between the source/drain region and the channel region. The well 58 has a first peak of an impurity concentration at a depth deeper than the pocket region 40 and shallower than the bottom of the source/drain regions 60, and a second peak of the impurity concentration at a depth near the bottom of the source/drain regions 60.

Abstract: The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.

Abstract: The semiconductor device comprises logic blocks 12 forming a logic circuit, and interconnection regions 14. A gate interconnection 32a including the gate electrode of a load transistor L1 and the gate electrode of a driver transistor D1, and the source/drain diffused layer 38 of a load transistor L2 are connected to each other by a conductor plug 50b. A gate interconnection 32b including the gate electrode of a load transistor L2 and the gate electrode of a driver transistor D2, and the source/drain diffused layer 35 of the load transistor L1 are connected to each other by a conductor plug 50c. The source/drain diffused layer 37 of a transfer transistor T1 and the source/drain diffused layer 37 of the first driver transistor D1 are made common, and the source/drain diffused layer 40 of the transfer transistor T2 and the source/drain diffused layer 40 of the driver transistor D2 are made common. Accordingly, the area for the memory cells to be formed in can be made very small.

Abstract: A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.

Abstract: A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: The semiconductor device comprises an interconnection buried in an interconnection groove formed in a lower insulating film, and an upper insulating film having a contact hole formed down to an end part of the interconnection. The interconnection groove is formed by using a design pattern having a main interconnection portion 100 and an extended portion 104 provided at an end part of a main interconnection portion 100 for forming the interconnection and extended perpendicularly to an extending direction of the main interconnection portion 100.

Abstract: Each of a plurality of repeating units comprises a plurality of memory cells. A second-conductivity-type well is formed in a surface layer of a semiconductor substrate extending over the plurality of the repeating units. In the second-conductivity-type well, first-conductivity-type channel MOS transistors of the plurality of the repeating units are provided. A second-conductivity-type well tap region is formed in one of the memory cells in each repeating unit and in the second-conductivity-type well. In the memory cell provided with the second-conductivity-type well tap region or in the memory cell adjacent thereto, an interlayer connection member is provided. The interlayer connection member is connected to the source region of one of the first-conductivity-type channel MOS transistors and to the corresponding second-conductivity-type well tap region.

Abstract: A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.

Abstract: Each of a plurality of repeating units comprises a plurality of memory cells. A second-conductivity-type well is formed in a surface layer of a semiconductor substrate extending over the plurality of the repeating units. In the second-conductivity-type well, first-conductivity-type channel MOS transistors of the plurality of the repeating units are provided. A second-conductivity-type well tap region is formed in one of the memory cells in each repeating unit and in the second-conductivity-type well. In the memory cell provided with the second-conductivity-type well tap region or in the memory cell adjacent thereto, an interlayer connection member is provided. The interlayer connection member is connected to the source region of one of the first-conductivity-type channel MOS transistors and to the corresponding second-conductivity-type well tap region.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: A method for preparing chloromethylphenylacetic acids represented by formula (II): wherein a methylphenylacetic acid represented by formula (I): is reacted with a chlorine gas, in an inert solvent, under the irradiation with light or in the presence of a radical initiator, is disclosed. According to the preparation method, high purity chloromethylphenylacetic acids can be prepared at a high yield, without using toxic sulfuryl chloride as a chlorinating agent, by chlorinating the methyl group of the methylphenylacetic acids at a high selectivity while suppressing by-production of a dichloro form or &agr;-chloro form.

Abstract: After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.