Patents by Inventor Yoshihisa Dotta
Yoshihisa Dotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11195965Abstract: Wires (22) electrically connecting solar cells (10) include first wires (22a) and second wires (22b). The first wires (22a) are connected to the first-conductivity-type electrodes (12) of a first one of the solar cells (10) and the second-conductivity-type electrodes (13) of a second one of the solar cells 10 that is adjacent to the first one of the solar cells (10). The second wires (22b) are connected to the second-conductivity-type electrodes (13) of the first one of the solar cells (10) and the first-conductivity-type electrodes (12) of the second one of the solar cells (10). The second wires (22b) are electrically separated by holes (21a) extending through both the second wires (22b) and an insulating base member (21).Type: GrantFiled: October 23, 2018Date of Patent: December 7, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihisa Dotta, Hajime Horinaka, Kohichi Katohno, Liumin Zou, Tetsuyoshi Inoue
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Publication number: 20190131466Abstract: Wires (22) electrically connecting solar cells (10) include first wires (22a) and second wires (22b). The first wires (22a) are connected to the first-conductivity-type electrodes (12) of a first one of the solar cells (10) and the second-conductivity-type electrodes (13) of a second one of the solar cells 10 that is adjacent to the first one of the solar cells (10). The second wires (22b) are connected to the second-conductivity-type electrodes (13) of the first one of the solar cells (10) and the first-conductivity-type electrodes (12) of the second one of the solar cells (10). The second wires (22b) are electrically separated by holes (21a) extending through both the second wires (22b) and an insulating base member (21).Type: ApplicationFiled: October 23, 2018Publication date: May 2, 2019Inventors: YOSHIHISA DOTTA, HAJIME HORINAKA, KOHICHI KATOHNO, LIUMIN ZOU, TETSUYOSHI INOUE
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Publication number: 20150287844Abstract: A solar battery module that can decrease the reduction in output is provided. The solar battery module (1) includes a solar battery panel (30) which includes: a solar battery cell (2) that includes an insulating passivation film (22) on a light reception surface; a translucent substrate (5) which is arranged on the side of the light reception surface of the solar battery cell; and a sealing member (4) which adheres the solar battery cell and the translucent substrate. A cell upper portion (4a) arranged on the light reception surface of the solar battery cell has an area resistivity of 1.36×1014 ?·cm2 or more.Type: ApplicationFiled: December 10, 2012Publication date: October 8, 2015Inventors: Yasushi Sainoh, Yoshihisa Dotta, Hiroyuki Ikawa, Masatomo Tanahashi, Shinji Nishioka, Kohei Sawada, Kentaro Usui, Tomoo Imataki, Hiroaki Itoh
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Publication number: 20120097245Abstract: Disclosed are a solar cell with an interconnection sheet, wherein at least either of the connection between a first conductive electrode of a back electrode type solar cell and a first conductive wire of an interconnection sheet and the connection between a second conductive electrode of the back electrode type solar cell and a second conductive wire of the interconnection sheet is electrically established by a conductive substance, and the conductive substance contains a metal which is in contact with at least either of the electrodes and the wires without metal bonding, a solar cell module containing the solar cell with an interconnection sheet, and a method for producing the solar cell with an interconnection sheet.Type: ApplicationFiled: June 18, 2010Publication date: April 26, 2012Inventors: Tomohiro Nishina, Yasushi Sainoo, Akiko Tsunemi, Yoshihisa Dotta
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Publication number: 20120085405Abstract: There is provided a back electrode type solar cell including a semiconductor substrate, and an electrode for first conduction type and an electrode for second conduction type disposed on one surface side of the semiconductor substrate, a center in a width direction of a first contact region, which is a region of the semiconductor substrate with which the electrode for first conduction type is in contact, being shifted in position from a center in a width direction of the electrode for first conduction type. There is also provided a solar cell with an interconnection sheet using the back electrode type solar cell, and a solar cell module using the back electrode type solar cell.Type: ApplicationFiled: June 9, 2010Publication date: April 12, 2012Inventors: Yoshihisa Dotta, Yasushi Sainoo, Akiko Tsunemi, Tomohiro Nishina
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Publication number: 20120037203Abstract: There is provided a wiring sheet (10) provided with a wiring (16) on an insulating base material (11) for electrically connecting a plurality of back electrode type solar cells (20), the wiring sheet (10) having a plurality of cell mounting portions (10a) provided with the back electrode type solar cells (20), the wiring sheet (10) being provided with an insulation layer (101) on a cell mounting side between adjacent cell mounting portions (10a). There is provided a wiring sheet (10) for a back electrode type solar cell, a solar cell with the wiring sheet, a solar cell module, and a method for fabricating the solar cell with the wiring sheet, that can reduce/prevent unwanted contact between the back electrode type solar cell (20) disposed on the wiring sheet (10) and the wiring (16) of the wiring sheet (10).Type: ApplicationFiled: April 5, 2010Publication date: February 16, 2012Inventors: Yasushi Sainoo, Yoshihisa Dotta, Akiko Tsunemi, Tomohiro Nishina
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Patent number: 7442642Abstract: The semiconductor device of the present invention and the method of the present invention, for forming the semiconductor device, form: a penetrating hole in a semiconductor wafer which has a first insulating film and an electrode pad formed on a first face of the semiconductor wafer, the penetrating hole being immediately below the electrode pad; and a second insulating film on an inner wall of the penetrating hole and on a second face of the semiconductor wafer. In forming the second insulating film, electrodeposition using the semiconductor wafer as a cathode is used. After the second insulating film is formed, the first insulating film is etched using the second insulating film as a mask, the back face of the electrode pad is exposed, and a conductor layer, acting as a penetrating electrode, is formed in the penetrating hole.Type: GrantFiled: September 16, 2005Date of Patent: October 28, 2008Assignee: Sharp Kabushiki KaishaInventor: Yoshihisa Dotta
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Patent number: 7365440Abstract: A semiconductor device includes a second insulating film formed on a second surface of a semiconductor substrate whose first surface has been formed with a first insulating film and an electrode pad, and an opening is made in a portion of the second insulating film directly below the electrode pad. By using the second insulating film as a mask, a through hole is formed in the semiconductor substrate in such a manner that the through hole recedes from an opening edge of the first insulating film. A third insulating film is formed only on the inner wall of the through hole.Type: GrantFiled: September 28, 2005Date of Patent: April 29, 2008Assignee: Sharp Kabushiki KaishaInventor: Yoshihisa Dotta
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Patent number: 7327041Abstract: A semiconductor package includes: a semiconductor chip having circuits formed on a surface, and having a thickness of 0.5 ?m or more and 100 ?m or less; and an adhesive resin layer provided so as to cover the surface of the semiconductor chip on which the circuits are provided.Type: GrantFiled: May 28, 2002Date of Patent: February 5, 2008Assignee: Sharp Kabushiki KaishaInventors: Yoshihisa Dotta, Kazuo Tamaki
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Patent number: 7276780Abstract: A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.Type: GrantFiled: June 20, 2006Date of Patent: October 2, 2007Assignee: Sharp Kabushiki KaishaInventors: Yoshihisa Dotta, Toshio Kimura
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Publication number: 20060231928Abstract: A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.Type: ApplicationFiled: June 20, 2006Publication date: October 19, 2006Applicant: Sharp Kabushiki KaishaInventors: Yoshihisa Dotta, Toshio Kimura
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Patent number: 7115972Abstract: A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.Type: GrantFiled: September 26, 2003Date of Patent: October 3, 2006Assignee: Sharp Kabushiki KaishaInventors: Yoshihisa Dotta, Toshio Kimura
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Patent number: 7052934Abstract: A fabrication method of a semiconductor device according to the present invention includes the steps of: bonding a reinforcing plate with a front surface of a semiconductor wafer via a reinforcing plate, the reinforcing plate having holes and the semiconductor wafer bearing semiconductor devices; grinding a back surface of the semiconductor wafer; and detaching the reinforcing plate from the semiconductor wafer by injecting a solvent for dissolving an adhesive layer into the holes and by allowing the solvent to permeate through the adhesive layer. The method enables the reinforcing plate to be quickly detached from the semiconductor wafer without causing defects, such as bending and cracking, in the semiconductor wafer after the reinforcing plate is used to grind the semiconductor wafer.Type: GrantFiled: February 27, 2004Date of Patent: May 30, 2006Assignee: Sharp Kabushiki KaishaInventors: Hideyuki Kurimoto, Yoshihisa Dotta, Toshio Kimura
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Publication number: 20060071347Abstract: In a semiconductor device and a fabrication method thereof according to the present invention, a second insulating film is formed on a second surface of a semiconductor substrate whose first surface has been formed with a first insulating film and an electrode pad, and an opening is made in a portion of the second insulating film directly below the electrode pad. By using the second insulating film as a mask, a through hole is formed in the semiconductor substrate in such a manner that the through hole recedes from an opening edge of the first insulating film. A third insulating film is formed only on the inner wall of the through hole. The opening edge of the second insulating film and the inner periphery surface of the third insulating film coincide as viewed from the second surface side of the semiconductor substrate.Type: ApplicationFiled: September 28, 2005Publication date: April 6, 2006Applicant: SHARP KABUSHIKI KAISHAInventor: Yoshihisa Dotta
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Publication number: 20060068580Abstract: The semiconductor device of the present invention and the method of the present invention, for forming the semiconductor device, form: a penetrating hole in a semiconductor wafer which has a first insulating film and an electrode pad formed on a first face of the semiconductor wafer, the penetrating hole being immediately below the electrode pad; and a second insulating film on an inner wall of the penetrating hole and on a second face of the semiconductor wafer. In forming the second insulating film, electrodeposition using the semiconductor wafer as a cathode is used. After the second insulating film is formed, the first insulating film is etched using the second insulating film as a mask, the back face of the electrode pad is exposed, and a conductor layer, acting as a penetrating electrode, is formed in the penetrating hole.Type: ApplicationFiled: September 16, 2005Publication date: March 30, 2006Applicant: Sharp Kabushiki KaishaInventor: Yoshihisa Dotta
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Patent number: 6847121Abstract: A semiconductor device includes, a circuit constituting section having a function circuit and an externally-drawing electrode, connected to the function circuit, on a surface of the circuit constituting section. An insulating layer is provided on a side of a rear surface of the circuit constituting section. The insulating layer has a face opposite to the circuit constituting section, which has an area that is larger than an area of the rear surface of the circuit constituting section.Type: GrantFiled: August 20, 2002Date of Patent: January 25, 2005Assignee: Sharp Kabushiki KaishaInventors: Yoshihisa Dotta, Kazuo Tamaki
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Publication number: 20040212086Abstract: A semiconductor apparatus includes (i) a semiconductor substrate, (ii) a field oxide film, formed in a surface of the semiconductor substrate, having an aperture section, (iii) a electrode pad formed on the field oxide film, and (iv) a penetration electrode electrically connected to the electrode pad via the aperture section of the field oxide film and a hole formed in the semiconductor substrate. The hole is formed in the aperture section of the field oxide film, when perpendicularly viewing the semiconductor substrate.Type: ApplicationFiled: April 21, 2004Publication date: October 28, 2004Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihisa Dotta, Toshio Kimura, Hideyuki Kurimoto
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Publication number: 20040188861Abstract: A fabrication method of a semiconductor device according to the present invention includes the steps of: bonding a reinforcing plate with a front surface of a semiconductor wafer via a reinforcing plate, the reinforcing plate having holes and the semiconductor wafer bearing semiconductor devices; grinding a back surface of the semiconductor wafer; and detaching the reinforcing plate from the semiconductor wafer by injecting a solvent for dissolving an adhesive layer into the holes and by allowing the solvent to permeate through the adhesive layer. The method enables the reinforcing plate to be quickly detached from the semiconductor wafer without causing defects, such as bending and cracking, in the semiconductor wafer after the reinforcing plate is used to grind the semiconductor wafer.Type: ApplicationFiled: February 27, 2004Publication date: September 30, 2004Applicant: SHARP KABUSHIKI KAISHAInventors: Hideyuki Kurimoto, Yoshihisa Dotta, Toshio Kimura
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Publication number: 20040080040Abstract: A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.Type: ApplicationFiled: September 26, 2003Publication date: April 29, 2004Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihisa Dotta, Toshio Kimura
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Publication number: 20040080045Abstract: A semiconductor device has multiple through electrodes with the same cross-sectional area extending through a semiconductor chip linking its front to back surface. The number of electrodes used is determined in accordance with the magnitude of the electric current for the same signal. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are readily capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.Type: ApplicationFiled: September 24, 2003Publication date: April 29, 2004Applicant: SHARP KABUSHIKI KAISHAInventors: Toshio Kimura, Yoshihisa Dotta